Renesas R5S72621 Manual De Usuario
Section 14 Realtime Clock
R01UH0134EJ0400 Rev. 4.00
Page 699 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
14.3.20
Frequency Register H/L (RFRH/L)
RFRH/L is a 16-bit readable/writable register.
The "frequency comparison value" is set in RFC[18:0] so that a 128-Hz clock is generated when
the realtime clock operates at the EXTAL clock frequency.
the realtime clock operates at the EXTAL clock frequency.
Change the "frequency comparison value" according to the EXTAL clock frequency. The
calculation method is shown below.
calculation method is shown below.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
Undefined
0
0
0
0
0
0
0
0
0
0
0
0
Undefined Undefined Undefined
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SEL64
-
-
-
-
-
-
-
RFC[15:0]
-
-
-
-
-
RFC[18:16]
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 SEL64 Undefined
R/W
64-Hz
Divider
Select
Indicates the operating clock that the EXTAL clock
frequency is dividable by 64-Hz and not dividable by
128-Hz.
128-Hz.
0: EXTAL clock frequency is dividable by 128-Hz.
1: EXTAL clock frequency is dividable by 64-Hz and not
dividable by 128-Hz.
Note: For 1-Mbyte version, this bit is reserved and
always read as 0. The write value should always
be 0.
be 0.
30 to 19
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
18, 17
RFC[18:17] Undefined R/W
Frequency comparison value
Sets the comparison value to generate operation clock
from the EXTAL clock frequency.
from the EXTAL clock frequency.
Note: For 1-Mbyte version, these bits are reserved
and always read as 0. The write value should
always be 0.
always be 0.