Renesas R5S72621 Manual De Usuario
Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00
Page 815 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
16.4.5
Data Format
The data format depends on the settings in the command register (SPCMD). Irrespective of
MSB/LSB first, this module treats the range from the LSB of the data register (SPDR) to the
assigned data length as transfer data.
MSB/LSB first, this module treats the range from the LSB of the data register (SPDR) to the
assigned data length as transfer data.
(1) MSB First Transfer (32-Bit Data)
Figure 16.8 shows the operation of the transmit buffer (SPTX) and the shift register when this
module performs a 32-bit data length MSB-first data transfer.
module performs a 32-bit data length MSB-first data transfer.
The CPU or direct memory access controller writes T31 to T00 to the transmit buffer of SPDR. If
the shift register is empty, this module copies the data in the transmit buffer to the shift register,
and fully populates the shift register. When serial transfer starts, this module outputs data from the
MSB (bit 31) of the shift register, and shifts in the data from the LSB (bit 0) of the shift register.
When the RSPCK cycle required for the serial transfer of 32 bits has passed, data R31 to R00 is
stored in the shift register. In this state, this module copies the data from the shift register to the
receive buffer, and empties the shift register. If the receive buffer does not have a space for the
receive data length after the receive data has been copied from the shift register to the receive
buffer, another serial transfer will not be started. In order to start another serial transfer, data for
the receive data length should be read from the receive buffer to secure the necessary space in the
receive buffer.
the shift register is empty, this module copies the data in the transmit buffer to the shift register,
and fully populates the shift register. When serial transfer starts, this module outputs data from the
MSB (bit 31) of the shift register, and shifts in the data from the LSB (bit 0) of the shift register.
When the RSPCK cycle required for the serial transfer of 32 bits has passed, data R31 to R00 is
stored in the shift register. In this state, this module copies the data from the shift register to the
receive buffer, and empties the shift register. If the receive buffer does not have a space for the
receive data length after the receive data has been copied from the shift register to the receive
buffer, another serial transfer will not be started. In order to start another serial transfer, data for
the receive data length should be read from the receive buffer to secure the necessary space in the
receive buffer.
If another serial transfer is started before the CPU or direct memory access controller writes to the
transmit buffer, received data R31 to R00 is shifted out from the shift register.
transmit buffer, received data R31 to R00 is shifted out from the shift register.