Renesas R5S72621 Manual De Usuario

 
Section 17   I

2

C Bus Interface 3 

Page 876 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

In slave receive mode, the master device outputs the transmit clock and transmit data, and the 
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to 
figures 17.11 and 17.12. The reception procedure and operations in slave receive mode are 
described below. 

1.  Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and 

TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 

2.  When the slave address matches in the first frame following detection of the start condition, 

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th 
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the 
read data show the slave address and R/W, it is not used.) 

3.  Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is 

fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be 
returned to the master device, is reflected to the next transmit frame. 

4.  The last byte data is read by reading ICDRR. 
 

ICDRS

ICDRR

1

2

1

3

4

5

6

7

8

9

9

A

A

RDRF

Data 1  

Data 2

Data 1 

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

SCL

(Slave output)

Bit 7

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

[2] Read ICDRR (dummy read)

[2] Read ICDRR

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