Renesas R5S72646 Manual De Usuario
Section 15 Serial Communication Interface with FIFO
R01UH0134EJ0400 Rev. 4.00
Page 773 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
D0
D1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 clocks
8 clocks
Base clock
Receive data
(RxD)
Start bit
–7.5 clocks
+7.5 clocks
Synchronization
sampling timing
Data sampling
timing
Figure 15.19 Receive Data Sampling Timing in Asynchronous Mode
(Operation on a Base Clock with a Frequency 16 Times the Bit Rate)
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = (0.5
− ) − (L − 0.5) F −
(1 + F)
× 100 %
1
2N
D
− 0.5
N
Where: M: Receive margin (
)
N: Ratio of clock frequency to bit rate (N = 16 or 8)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0, D = 0.5 and N = 16, the receive margin is 46.875
, as given by
equation 2.
Equation 2:
When D = 0.5 and F = 0:
M = (0.5
− 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20
to 30.