Intel Xeon E7420 AD80583QH0468M Hoja De Datos

Intel® Xeon® Processor 7400 Series Datasheet

83

D[63:0]#

I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path 

between the processor FSB agents, and must connect the appropriate pins on all 

such agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals, and will thus be driven four times 

in a common clock period. D[63:0]# are latched off the falling edge of 

both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals 

correspond to a pair of one DSTBP# and one DSTBN#. The following 

table shows the grouping of data signals to strobes and DBI#.

Furthermore, the DBI# signals determine the polarity of the data 

signals. Each group of 16 data signals corresponds to one DBI# signal. 

When the DBI# signal is active, the corresponding data group is 

inverted and therefore sampled active high. 

DBI[3:0]#

I/O

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity 

of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the 

data bus is inverted. If more than half the data bits, within, within a 16-bit group, 

would have been asserted electronically low, the bus agent may invert the data 

bus signals for that particular sub-phase for that 16-bit group.

DBSY#

I/O

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on 

the processor FSB to indicate that the data bus is in use. The data bus is released 

after DBSY# is deasserted. This signal must connect the appropriate pins on all 

processor FSB agents.

DEFER#

I

DEFER# is asserted by an agent to indicate that a transaction cannot be 

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility 

of the addressed memory or I/O agent. This signal must connect the appropriate 

pins of all processor FSB agents.

DP[3:0]#

I/O

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They 

are driven by the agent responsible for driving D[63:0]#, and must connect the 

appropriate pins of all processor FSB agents.

DRDY#

I/O

DRDY# (Data Ready) is asserted by the data driver on each data transfer, 

indicating valid data on the data bus. In a multi-common clock data transfer, 

DRDY# may be deasserted to insert idle clocks. This signal must connect the 

appropriate pins of all processor FSB agents.

D[15:0]#

0

0

D[31:16]#

1

1

D[47:32]#

2

2

D[63:48]#

3

3

DBI0#

D[15:0]#

DBI1#

D[31:16]#

DBI2#

D[47:32]#

DBI3#

D[63:48]#