Crown k1 Manual Suplementario
K Series Service Manual
Rev A.
3-2 Theory
©1999 Crown International, Inc.
c. T1 secondary#2: After rectification (D14 and D15)
and filtering (C29 and C30) B2+7 and B2-7
d. T1 secondary#3: After rectification (D16 and D17)
and filtering (C31 and C32) B1+7 and B1-7
4. Oscillator Sync: the final destination of the 125KHz
signal is to synchronize the original 125KHz oscillator
U9.
signal is to synchronize the original 125KHz oscillator
U9.
3.2 Input Stage
Both XLR and phone jack input connectors are in par-
allel with each other. While in most audio products
the incoming shield is tied to the amplifiers ground
network,
allel with each other. While in most audio products
the incoming shield is tied to the amplifiers ground
network,
K Series amplifiers insert a 24 ohm resistor
(R100) paralleled with two .01uf capacitors(C100 and
C135) for the purpose of inhibiting ground loop circu-
lating currents and RFI protection.
C135) for the purpose of inhibiting ground loop circu-
lating currents and RFI protection.
The signal is fed to the balanced to unbalanced gain
stage. Input impedance is 20K ohm balanced and
10K ohm unbalanced.
stage. Input impedance is 20K ohm balanced and
10K ohm unbalanced.
K Series amplifiers come with two input sensitivity se-
lections: 26dB and 1.4V. With the gain switch (S100)
out the inverting gain stage is unity (gain of 1). With
the gain switch (S100) in the inverting gain stage adds
(depending on the amplifier model) the necessary
gain to achieve 1.4V input sensitivity.
lections: 26dB and 1.4V. With the gain switch (S100)
out the inverting gain stage is unity (gain of 1). With
the gain switch (S100) in the inverting gain stage adds
(depending on the amplifier model) the necessary
gain to achieve 1.4V input sensitivity.
Inherent within all PWM amplifiers is a rise in gain at
higher frequencies. Because of this a 7th order
Gaussian low pass filter has been included in the in-
put stage of the
higher frequencies. Because of this a 7th order
Gaussian low pass filter has been included in the in-
put stage of the
K Series amplifiers. This Gaussian
filter is found immediately after the gain stage. U103A,
U103B, U103C, U103D comprise this filter. U101D and
R172 form the gain calibration stage for this 7th order
Gaussian filter.
U103B, U103C, U103D comprise this filter. U101D and
R172 form the gain calibration stage for this 7th order
Gaussian filter.
3.3 DC Servo
Because the K series of amplifiers are DC coupled
from the Gaussian Filter through to the amplifier out-
put DC offset voltages can appear. This DC voltage
can be amplified and the audio signal ride on top shift-
ing its reference point resulting in nonsymmetrical clip-
ping. For this reason a DC correction circuit has been
added. The non-inverting input of U105 is tied to the
speaker output.
from the Gaussian Filter through to the amplifier out-
put DC offset voltages can appear. This DC voltage
can be amplified and the audio signal ride on top shift-
ing its reference point resulting in nonsymmetrical clip-
ping. For this reason a DC correction circuit has been
added. The non-inverting input of U105 is tied to the
speaker output.
Since the purpose of U105 is to compensate for DC
offset voltages elimination of any AC signal is para-
offset voltages elimination of any AC signal is para-
mount. There are three filters that eliminate any AC
component:
component:
1. R147 and C121 for a 1 pole filter (-3 point is 8Hz).
2. The RC networks C114/R141 and C118/R148 each
form a single pole filter.
form a single pole filter.
The combination of all three filters form a three-pole
filter leaving only the DC voltage.
filter leaving only the DC voltage.
3.4 Sleep Circuit
The sleep circuit monitors each channel for a signal.
When no signal is present for approximately six sec-
onds the sleep circuit sends a Standby signal to the
main module turning off the carrier frequency within
the modulator circuit. It takes approximately 0.5mV of
input signal to bring the amplifier out of Sleep mode.
When no signal is present for approximately six sec-
onds the sleep circuit sends a Standby signal to the
main module turning off the carrier frequency within
the modulator circuit. It takes approximately 0.5mV of
input signal to bring the amplifier out of Sleep mode.
Signal is sampled from the second stage (U103A pin
1) of the Gaussian low pass filter. U5D generates the
Standby control signal to place the amplifier in sleep
mode. R17, R15 and C7 form the RC timing network
that determines the time of switching states of U5D
from +0.9V (awake) and –13V (asleep). The Standby
control signal is routed to the base of Q102 through
the diode D111.
1) of the Gaussian low pass filter. U5D generates the
Standby control signal to place the amplifier in sleep
mode. R17, R15 and C7 form the RC timing network
that determines the time of switching states of U5D
from +0.9V (awake) and –13V (asleep). The Standby
control signal is routed to the base of Q102 through
the diode D111.
3.5 Error Amp
The audio signal enters the main module from the in-
put module. the audio and negative feedback signals
are both processed by the error amplifier U100D. From
the error amplifier the signal is divided and is fed to
the modulator. Since the modulator circuit is balanced
the drive signal for the positive modulator is inverted
by U100C.
put module. the audio and negative feedback signals
are both processed by the error amplifier U100D. From
the error amplifier the signal is divided and is fed to
the modulator. Since the modulator circuit is balanced
the drive signal for the positive modulator is inverted
by U100C.
3.6 Modulator
U101 and U103 are high speed differential compara-
tors. The comparator section has two outputs: invert-
ing and non-inverting. Therefore the output is bal-
anced. The audio signal is applied to the inverting
input of both differential comparators. The 250KHz
triangle wave is applied to the non-inverting input of
both differential comparators. With no audio signal the
250KHz is passed on to the NAND gate section of the
differential comparator unchanged. Each NAND gate
has two inputs: the modulated signal from the high
speed comparater section and current limiter
signal(U6A). In the event of over current the current
limiter (U6A) signal is shut off disabling the NAND
tors. The comparator section has two outputs: invert-
ing and non-inverting. Therefore the output is bal-
anced. The audio signal is applied to the inverting
input of both differential comparators. The 250KHz
triangle wave is applied to the non-inverting input of
both differential comparators. With no audio signal the
250KHz is passed on to the NAND gate section of the
differential comparator unchanged. Each NAND gate
has two inputs: the modulated signal from the high
speed comparater section and current limiter
signal(U6A). In the event of over current the current
limiter (U6A) signal is shut off disabling the NAND