Intel Xeon X3460 BX80605X3460 Manual De Usuario
Los códigos de productos
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
123
Processor Integrated I/O (IIO) Configuration Registers
3.4.4.30
VTGENCTRL—Intel
®
VT-d General Control Register
Register:
VTGENCTRL
Device: 8
Function: 0
Offset:
184h
Bit
Attr
Default
Description
15
RWO
0b
Lock Intel VT-d
When this bit is 0, the VTBAR[0] is RWL (where the lock functionality is
When this bit is 0, the VTBAR[0] is RWL (where the lock functionality is
described in VTBAR register). When this bit is 0, VTBAR[0] is RO.
14:11
RV
0h
Reserved
10:8
RWL
111b
Isoch GPA_LIMIT
Represents the guest virtual addressing limit for the Isoch Intel VT-d
Represents the guest virtual addressing limit for the Isoch Intel VT-d
engine.
000–011 = Reserved
100 = 2^36 (that is, Bits 35:0)
101 = 2^37
110 = 2^38
111 = 2^39
When Intel VT-d translation is enabled on the isoch Intel VT-d engine, all
000–011 = Reserved
100 = 2^36 (that is, Bits 35:0)
101 = 2^37
110 = 2^38
111 = 2^39
When Intel VT-d translation is enabled on the isoch Intel VT-d engine, all
incoming guest addresses from isochronous device, that go beyond the
limit specified in this register will be aborted by the IIO and a UR response
returned. This register is not used when translation is not enabled. Note
that ‘translated’ and ‘pass-through’ addresses are in the ‘host-addressing’
domain and NOT ‘guest-addressing’ domain and hence GPA_LIMIT checking
on those accesses are bypassed and instead HPA_LIMIT checking applies.
This field may be locked as RO in Intel
This field may be locked as RO in Intel
TXT mode.
7:4
RWL
0h
Isoch/Non-Isoch HPA_LIMIT
Represents the host processor addressing limit
0000 = 2^36 (that is, Bits 35:0)
0001 = 2^37 (that is, Bits 36:0)
...
1111 = 2^51 (that is, Bits 50:0)
When Intel VT-d translation is enabled on an Intel VT-d engine (isoch or
Represents the host processor addressing limit
0000 = 2^36 (that is, Bits 35:0)
0001 = 2^37 (that is, Bits 36:0)
...
1111 = 2^51 (that is, Bits 50:0)
When Intel VT-d translation is enabled on an Intel VT-d engine (isoch or
non-isoch), all host addresses (during page walks) that go beyond the limit
specified in this register will be aborted by IIO. Note that pass-through
accesses carry the host-address directly in the access and are subject to
this check as well..
This field may be locked as RO in Intel
This field may be locked as RO in Intel
TXT mode.
3:0
RWL
8h
Non-Isoch GPA_LIMIT
Represents the guest virtual addressing limit for the non-Isoch Intel VT-d
Represents the guest virtual addressing limit for the non-Isoch Intel VT-d
engine.
0000 = 2^40 (that is, Bits 39:0)
0001 = 2^41 (that is, Bits 40:0)
0000 = 2^40 (that is, Bits 39:0)
0001 = 2^41 (that is, Bits 40:0)
0111 = 2^47
1000 = 2^48
1001–1111 = Reserved
When Intel VT-d translation is enabled, all incoming guest addresses from
1000 = 2^48
1001–1111 = Reserved
When Intel VT-d translation is enabled, all incoming guest addresses from
PCI Express, associated with the non-isoch Intel VT-d engine, that go
beyond the limit specified in this register will be aborted by IIO and a UR
response returned. This register is not used when translation is not
enabled. Note that ‘translated’ and ‘pass-through’ addresses are in the
‘host-addressing’ domain and NOT ‘guest-addressing’ domain and hence
GPA_LIMIT checking on those accesses are bypassed and instead
HPA_LIMIT checking applies.
This field may be locked as RO in Intel
This field may be locked as RO in Intel
TXT mode