Intel Xeon X3460 BX80605X3460 Manual De Usuario
Los códigos de productos
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
175
Processor Integrated I/O (IIO) Configuration Registers
14:12
RWDS
1/2h
VN0 - DRS credits
With Isoc enabled this value is expected to be set at 4 to ensure QoS with
With Isoc enabled this value is expected to be set at 4 to ensure QoS with
processor.
Allowed values = 0-7 credits
Allowed values = 0-7 credits
11
RV
0
Reserved
10:8
RWDS
0/2h
VN0 - Snp credits
Allowed values = 0-7 credits
Snp credits are only needed for debug mode only. This should be set to 0 for
Allowed values = 0-7 credits
Snp credits are only needed for debug mode only. This should be set to 0 for
normal operation. It can be changed to 1 for debug mode.
7
RV
0
Reserved
6:0
RWDS
66/4Ah
VNA credits
Default is set to 102 (66h), which allows for 1 VN0 credit per message class
Default is set to 102 (66h), which allows for 1 VN0 credit per message class
to be assigned with standard headers.
0 - 127 credits
Additional modifiers on VNA credits.
If VN0 Snp Credits is set to 1, this must be set to one less credit.
If VN0 DRS credits are set to the recommended isoc value (4), this should be
0 - 127 credits
Additional modifiers on VNA credits.
If VN0 Snp Credits is set to 1, this must be set to one less credit.
If VN0 DRS credits are set to the recommended isoc value (4), this should be
set to 33 less credits.
Register: QPI[0]LCRDC
Device:
16
Function: 0
Offset: F8h
Bit
Attr
Default
Description