Intel Xeon X3460 BX80605X3460 Manual De Usuario
Los códigos de productos
BX80605X3460
Processor Integrated I/O (IIO) Configuration Registers
36
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
(Sheet 1 of 2)
Register:
PCICMD
Device:
3-6 (PCIe*)
Function: 0
Offset:
04h
Bit
Attr
Default
Description
15:11
RV
00h
Reserved (by PCI SIG)
10
RW
0
Legacy Interrupt Mode Enable/Disable
9
RO
0
Fast Back-to-Back Enable
Not applicable to PCI Express and is hardwired to 0.
Not applicable to PCI Express and is hardwired to 0.
8
RW
0
SERR Enable
For PCI Express/DMI ports, this field enables notifying the internal core
For PCI Express/DMI ports, this field enables notifying the internal core
error logic of occurrence of an uncorrectable error (fatal or non-fatal) at
the port. The internal core error logic of IIO then decides if/how to
escalate the error further (pins/message, and so forth). This bit also
controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL
messages received from the port to the internal IIO core error logic.
0 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
0 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is disabled.
1 = Fatal and Non-fatal error generation and Fatal and Non-fatal error
message forwarding is enabled.
Refer to the latest PCI Express Base Specification for details of how this
bit is used in conjunction with other control bits in the Root Control
register for forwarding errors detected on the PCI Express interface to
the system core error logic.
7
RO
0
IDSEL Stepping/Wait Cycle Control
Not applicable to Processor Integrated I/O devices.
Not applicable to Processor Integrated I/O devices.
Hardwired to 0.
6
RW
0
Parity Error Response
For PCI Express/DMI ports, Processor Integrated I/O ignores this bit and
For PCI Express/DMI ports, Processor Integrated I/O ignores this bit and
always does ECC/parity checking and signaling for data/address of
transactions both to and from Integrated I/O.
5
RO
0
VGA Palette Snoop Enable
Not applicable to Processor Integrated I/O devices.
Not applicable to Processor Integrated I/O devices.
Hardwired to 0.
4
RO
0
Memory Write and Invalidate Enable
Not applicable to Processor Integrated I/O devices.
Not applicable to Processor Integrated I/O devices.
Hardwired to 0.
3
RO
0
Special Cycle Enable
Not applicable to PCI Express. Hardwired to 0.
Not applicable to PCI Express. Hardwired to 0.
2
RW
0
Bus Master Enable (BME)
Controls the ability of the PCI Express port in generating/forwarding
Controls the ability of the PCI Express port in generating/forwarding
memory (including MSI writes) or I/O transactions (and not messages)
or configuration transactions from the secondary side to the primary
side.
0 = The Bus Master is disabled. When this bit is 0, Integrated I/O root
0 = The Bus Master is disabled. When this bit is 0, Integrated I/O root
ports will treat upstream PCI Express memory writes/reads, I/O
writes/reads, and configuration reads and writes as unsupported
requests (and follow the rules for handling unsupported requests).
This behavior is also true towards transactions that are already
pending in the Integrated I/O root port’s internal queues when the
BME bit is turned off.
1 = Enables the PCI Express ports to generate/forward memory,
configuration, or I/O read/write requests.