Intel Xeon X3460 BX80605X3460 Manual De Usuario

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

99

The PCI Status register is a 16-bit status register that typically reports the occurrence 
of various events associated with the primary side of the “virtual” PCI Express device. 
Since these devices are host bridge devices, the only field that has meaning is 
“Capabilities List.”

0

RO

0

IO Space Enable
Applies only to PCI Express/DMI ports 
0 = Disables the I/O address range, defined in the IOBASE and IOLIM 

registers of the PCI-to-PCI bridge header, for target decode from 

primary side.

1 = Enables the I/O address range, defined in the IOBASE and IOLIM 

registers of the PCI-to-PCI bridge header, for target decode from 

primary side.

Note that if a PCI Express/DMI port’s IOSE bit is clear, that port can still be 

target of an I/O transaction if subtractive decoding is enabled on that port.

15

RO

0

Detected Parity Error
This bit is set by a device when it receives a packet on the primary side with 

an uncorrectable data error or an uncorrectable address/control parity error. 

The setting of this bit is regardless of the Parity Error Response bit (PERRE) 

in the PCICMD register.

14

RO 0

Signaled System Error 
0 = The device did not report a fatal/non-fatal error

1 = The device reported fatal/non-fatal (and not correctable) errors it 

detected on its PCI Express interface. Software clears this bit by writing 

a 1 to it. For Express ports, this bit is also set (when SERR enable bit is 

set) when a FATAL/NON-FATAL message is forwarded from the Express 

link 

13

RO 

0

Received Master Abort
This bit is set when a device experiences a master abort condition on a 

transaction it mastered on the primary interface (Integrated I/O internal 

bus). Note that certain errors might be detected right at the PCI Express 

interface and those transactions might not ‘propagate’ to the primary 

interface before the error is detected (for example, accesses to memory 

above TOCM in cases where the PCI Express interface logic itself might have 

visibility into TOCM). Such errors do not cause this bit to be set, and are 

reported using the PCI Express interface error bits (secondary status 

register). Conditions that cause Bit 13 to be set, include:

• Device receives a completion on the primary interface (internal bus of 

Integrated I/O) with Unsupported Request or master abort completion 

Status. This includes UR status received on the primary side of a PCI 

Express port on peer-to-peer completions also. 

• Device accesses to holes in the main memory address region that are 

detected by Intel QuickPath Interconnect Source Address Decoder.

• Other master abort conditions detected on the Integrated I/O internal 

bus.