Intel Xeon X3460 BX80605X3460 Manual De Usuario
Los códigos de productos
BX80605X3460
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
19
Configuration Process and Registers
2
Configuration Process and
Registers
2.1
Platform Configuration Structure
The DMI physically connects the processor and the Intel Platform Controller Hub (PCH).
From a configuration standpoint, the DMI is logically PCI Bus 0. A physical PCI Bus 0
does not exist. DMI and the internal devices in the processor Integrated I/O (IIO) and
Intel PCH logically constitute PCI Bus 0 to configuration software. As a result, all
devices internal to the processor and the Intel PCH appear to be on PCI Bus 0.
From a configuration standpoint, the DMI is logically PCI Bus 0. A physical PCI Bus 0
does not exist. DMI and the internal devices in the processor Integrated I/O (IIO) and
Intel PCH logically constitute PCI Bus 0 to configuration software. As a result, all
devices internal to the processor and the Intel PCH appear to be on PCI Bus 0.
The system primary PCI expansion bus is physically attached to the Intel PCH and,
from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-
PCI bridge and, therefore, has a programmable PCI Bus number. The PCI Express*
Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI
bridge that is a device resident on PCI Bus 0.
from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-
PCI bridge and, therefore, has a programmable PCI Bus number. The PCI Express*
Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI
bridge that is a device resident on PCI Bus 0.
Devices residing in the Processor Uncore appear on PCI Bus FFh. There is a
programmable base bus number that determines the top bus number to start top down
processor socket to PCI bus mapping. The processors default to 255 as the top bus
number. However, this top bus number can be redefined by the SAD_PCIEXBAR CSR
(Bus: FFh, Device 0, Function 1, Register offset 50h).
programmable base bus number that determines the top bus number to start top down
processor socket to PCI bus mapping. The processors default to 255 as the top bus
number. However, this top bus number can be redefined by the SAD_PCIEXBAR CSR
(Bus: FFh, Device 0, Function 1, Register offset 50h).
2.1.1
Processor Integrated I/O (IIO) Devices (PCI Bus 0)
The processor IIO contains the following PCI devices within a single, physical
component. The configuration registers for the devices are mapped as devices residing
on PCI Bus 0.
component. The configuration registers for the devices are mapped as devices residing
on PCI Bus 0.
• Device 0 — DMI Root Port. Logically this appears as a PCI device residing on PCI
Bus 0. Device 0 contains the standard PCI header registers, extended PCI
configuration registers and DMI device specific configuration registers.
configuration registers and DMI device specific configuration registers.
• Device 3 — PCI Express Root Port 1. Logically this appears as a “virtual” PCI-to-
PCI bridge residing on PCI Bus 0 and is compliant with the PCI Express Local Bus
Specification Revision 1.0. Device 3 contains the standard PCI Express/PCI
configuration registers including PCI Express Memory Address Mapping registers. It
also contains the extended PCI Express configuration space that includes PCI
Express error status/control registers and Isochronous and Virtual Channel
controls.
Specification Revision 1.0. Device 3 contains the standard PCI Express/PCI
configuration registers including PCI Express Memory Address Mapping registers. It
also contains the extended PCI Express configuration space that includes PCI
Express error status/control registers and Isochronous and Virtual Channel
controls.
• Device 4 — PCI Express Root Port 2. Logically this appears as a “virtual” PCI-to-
PCI bridge residing on PCI bus 0 and is compliant with PCI Express Specification
Revision 1.0. Device 4 contains the standard PCI Express/PCI configuration
registers including PCI Express Memory Address Mapping registers. It also contains
the extended PCI Express configuration space that includes PCI Express Link
status/control registers and Isochronous and Virtual Channel controls.
Revision 1.0. Device 4 contains the standard PCI Express/PCI configuration
registers including PCI Express Memory Address Mapping registers. It also contains
the extended PCI Express configuration space that includes PCI Express Link
status/control registers and Isochronous and Virtual Channel controls.
• Device 5 — PCI Express Root Port 3. Logically this appears as a “virtual” PCI-to-
PCI bridge residing on PCI Bus 0 and is compliant with PCI Express Local Bus
Specification Revision 1.0. Device 5 contains the standard PCI Express/PCI
configuration registers including PCI Express Memory Address Mapping registers. It
also contains the extended PCI Express configuration space that include PCI
Express error status/control registers and Isochronous and Virtual Channel
controls.
Specification Revision 1.0. Device 5 contains the standard PCI Express/PCI
configuration registers including PCI Express Memory Address Mapping registers. It
also contains the extended PCI Express configuration space that include PCI
Express error status/control registers and Isochronous and Virtual Channel
controls.