3com 3031 Instruccion De Instalación
142
C
HAPTER
14: WAN I
NTERFACE
C
ONFIGURATION
“TxClk” represents transmitting clock and “RxClk” receiving clock. The clock ahead
of “=” is the DTE clock and the one behind is the DCE clock.
of “=” is the DTE clock and the one behind is the DCE clock.
Perform the following configuration in synchronous serial interface view.
By default,
dceclk
and
dteclk3
are respectively selected for the synchronous
serial interfaces at DCE side and DTE side.
Setting clock inversion
In some special cases, the clock will generate half-period delay on the line, which
may cause failed interconnection of equipment at two ends or large amount of
messages discarded. In this case, the transmitting clock signal of DTE-side
synchronous serial interface can be inverted to eliminate the influence of the delay.
may cause failed interconnection of equipment at two ends or large amount of
messages discarded. In this case, the transmitting clock signal of DTE-side
synchronous serial interface can be inverted to eliminate the influence of the delay.
Perform the following configuration in synchronous serial interface view.
By default, clock signal inversion is disabled.
This command can take effect only on some clock signals generated by some DCE
devices. In addition, clock inversion should not set for common applications.
devices. In addition, clock inversion should not set for common applications.
Enabling/Disabling level detection
When determining whether a synchronous serial interface is UP or DOWN, the
system will by default detect the DSR signal, DCD signal, and the signal of the
external cable connection state. The synchronous serial interface will be regarded
up only when all these three signals are valid. Otherwise, it will be regarded down.
If level detection has been disabled on a synchronous serial interface, the system
system will by default detect the DSR signal, DCD signal, and the signal of the
external cable connection state. The synchronous serial interface will be regarded
up only when all these three signals are valid. Otherwise, it will be regarded down.
If level detection has been disabled on a synchronous serial interface, the system
Table 160 Clock options available for a synchronous serial interface working as DTE
Clock option
Description
DTE1
TxClk = TxClk, RxClk = RxClk
DTE2
TxClk = TxClk, RxClk = TxClk
DTE3
TxClk = RxClk, RxClk = TxClk
DTE4
TxClk = RxClk, RxClk = RxClk
Table 161 Selecting operating clock
Operation
Command
Set the clock for the synchronous serial interface
working as DCE.
working as DCE.
clock dceclk
Select an operating clock for the synchronous serial
interface working as DTE.
interface working as DTE.
clock { dteclk1 | dteclk2 |
dteclk3 | dteclk4 }
dteclk3 | dteclk4 }
Table 162 Setting clock inversion
Operation
Command
Enable the inversion of transmitting clock signal
generated by the synchronous serial interface at DTE
side.
generated by the synchronous serial interface at DTE
side.
invert transmit-clock
Disable the inversion of transmitting clock signal
generated by the synchronous serial interface at DTE
side.
generated by the synchronous serial interface at DTE
side.
undo invert transmit-clock