Cisco Cisco Packet Data Gateway (PDG) Guía De Instalación
Technical Specifications
▀ Interface Specifications
▄ ASR 5000 Installation Guide
270
BITS Timing Interface
Important:
External Building Interface Timing Supply (BITS) timing is an alternative to using clock signals
derived from an ATM port on an OLC/OLC2, or an ANSI SONET STS-3/SDH STM-1 port on a CLC/CLC2 to
synchronize line card timing. (Line-derived clocking requires that the SPIO be equipped with the optional Stratum 3
clock module.)
synchronize line card timing. (Line-derived clocking requires that the SPIO be equipped with the optional Stratum 3
clock module.)
BITS E1 BNC Interface
The BNC version of the SPIO employs a 75-ohm coaxial BNC connector that accepts an analog E1 BITS signal from
which the SPIO derives a 2048 kHz clock. The following figure shows the BITS BNC timing interface.
which the SPIO derives a 2048 kHz clock. The following figure shows the BITS BNC timing interface.
Figure 66. SPIO E1 BITS BNC Pinout
BITS T1 3-Pin Interface
The 3-pin version of the SPIO employs a wire-wrap connector that accepts a T1 (DS1) BITS data signal (all ones) from
which the SPIO derives a 1544 kHz clock. The following figure shows the BITS 3-wire timing interface wire-wrap pin-
out.
which the SPIO derives a 1544 kHz clock. The following figure shows the BITS 3-wire timing interface wire-wrap pin-
out.
Figure 67. SPIO T1 BITS Wire-Wrap Pinout