Intel D425 AU80610006252AA Manual De Usuario
Los códigos de productos
AU80610006252AA
Processor Configuration Registers
110
Datasheet
1.9.8
MLT2 - Master Latency Timer
B/D/F/Type: 0/2/0/PCI
Address Offset:
Dh
Default Value:
00h
Access:
RO;
Size: 8
bits
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
does not perform bursts.
Bit Acces
s
Default
Value
Description
7:0 RO 00h
Master Latency Timer Count Value (MLTCV):
Hardwired to 0s.
Hardwired to 0s.
1.9.9
HDR2 - Header Type
B/D/F/Type: 0/2/0/PCI
Address Offset:
Eh
Default Value:
80h
Access:
RO;
Size: 8
bits
This register contains the Header Type of the IGD.
Bit Access Default
Value
Description
7 RO 1b
Multi Function Status (MFUNC):
Indicates if the device is a Multi-Function
Device. The Value of this register is determined
by Device #0, offset 54h, DEVEN[4]. If Device
#0 DEVEN[4] is set, the MFUNC bit is also set.
Indicates if the device is a Multi-Function
Device. The Value of this register is determined
by Device #0, offset 54h, DEVEN[4]. If Device
#0 DEVEN[4] is set, the MFUNC bit is also set.
6:0 RO 00h
Header Code (H):
This is a 7-bit value that indicates the Header
Code for the IGD. This code has the value 00h,
indicating a type 0 configuration space format.
This is a 7-bit value that indicates the Header
Code for the IGD. This code has the value 00h,
indicating a type 0 configuration space format.
1.9.10
MMADR - Memory Mapped Range Address
B/D/F/Type: 0/2/0/PCI
Address Offset:
Address Offset:
10-13h
Default Value:
00000000h
Access:
RO; RW;
Size: 32
bits
This register requests allocation for the IGD registers and instruction ports. The
allocation is for 512 KB and the base address is defined by bits [31:19].
allocation is for 512 KB and the base address is defined by bits [31:19].