Intel 2 Duo E7200 AT80571PH0613M Hoja De Datos
Los códigos de productos
AT80571PH0613M
Electrical Specifications
34
Datasheet
5.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
6.
Duty Cycle (High time/Period) must be between 40 and 60%
§ §
Figure 4.
Differential Clock Waveform
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback
BCLK0
BCLK1
Tph
Tpl
Tp
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
V
CROSS (ABS
)
V
CROSS (ABS
)
Figure 5.
Measurement Points for Differential Clock Waveforms
+150 mV
-150 mV
0.0V
0.0V
Slew_rise
+150mV
-150mV
V_swing
Slew _fall
Diff
T5 = BCLK[1:0] rise and fall time through the swing region