Intel AT80604005280AA Manual De Usuario
Intel® Xeon® Processor 7500 Datasheet, Volume 1
109
Signal Definitions
FBD1SBOCLK[C/D][P/N]0
O
These differential pair output clock signals generated from Intel® Xeon® processor
7500 series are inputs to the branch one, channel C and D of Intel® Scalable
Memory Interconnects.
Example: FBD1SBICLKAP0 Intel® Scalable Memory Interconnect branch 1, south
bound clock output signal of channel A and positive bit of the differential pair.
FLASHROM_CFG[2:0]
I
These are input signals to the Intel® Xeon® processor 7500 series that would
initialize and map the serial Flash ROM upon reset. After the reset is deasserted this
input would be ignored by the processor logic.
FLASHROM_CLK
O
Serial flash ROM clock.
FLASHROM_CS[3:0]_N
O
Serial Flash ROM chip selects. Up to four separate flash ROM parts may be used.
FLASHROM_DATI
I
Serial Data Input (from ROM(s) to processor).
FLASHROM_DATO
O
Serial Data Output (from processor to ROM(s)).
FLASHROM_WP_N
O
Flash ROM write-protect.
FORCE_PR_N
I
Force processor power reduction by activation of a TCC.
ISENSE_D[N/P]
O
Current sense voltage input for Vcore VR11.1
LT-SX (Test-Lo)
I
In platforms supporting the LT-SX feature, the LT-SX pin on the processor should be
variable setting and driven based on the processor type installed. With the follow on
processor installed, the LT-SX pin should be driven high to support LT-SX. With the
Intel® Xeon® processor 7500 series installed the LT-SX pin should be driven low.
Note that LT-SX is not supported on the Intel® Xeon® processor 7500 series. On
platforms not supporting the LT-SX feature, the pin can be strapped low. For Intel®
Xeon® processor 7500 series debug purposes, you will need that ability to pull LT-SX
low.
MBP[7:0]
IO
Sideband signals connecting to XDP header for Run-time control and debug.
MEM_THROTTLE[1:0]_N
I
When asserted, the internal memory controllers throttle the memory command issue
rate to a configurable fraction of the nominal command rate settings.
MEM_Throttle[1] corresponds to mem_ctrl behind the HA xxx 11, and
MEM_Throttle[0] corresponds to mem_ctrl behind HA xxx 01.
NMI
I
Interrupt input. Active high. Must be minimum of three clocks.
PECI
IO
Processor Sideband Access via PECI interface.
PRDY_N
O
Processor Debug interface.
PREQ_N
I
Processor Debug interface.
Proc_ID[1:0]
O
Processor ID. 11: Intel® Xeon® processor 7500 series. 10: Refresh CPU. 01, 00:
Reserved for future generations.
PROCHOT_N
O
The assertion of PROCHOT_N (processor hot) indicates that the processor die
temperature has reached its thermal limit. Open Drain Output.
PSI_CACHE_N
O
Vcache Power Status Indicator signal to the VR that the processor is in a low power
state so the VR can use fewer phases. This signal has on die termination of 50 Ohms.
PSI_N
O
Vcore Power Status Indicator signal to the VR that the processor is in a low power
state so the VR can use fewer phases. This signal has on die termination of 50 Ohms.
Table 5-1.
Signal Definitions (Sheet 3 of 6)
Name
Type
Description
Intel®
SMI
1
SB
O
CLK
C/D
P/N
Interface
Name
Branch
Number
South
Bound
Output
Clock
Channel Differential
Pair
Polarity
Polarity
Positive/
Negative