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LF80550KG096007
Intel® Xeon® Processor 7400 Series Datasheet
11
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Commonly used terms are explained here for clarification:
• Intel® Xeon® Processor 7400 Series – Intel 64-bit microprocessor intended for
multi processor servers. The Intel® Xeon® Processor 7400 Series is a single die
implementation based on Intel’s 45 nanometer process, in the FC-mPGA8 package
with four or six processor cores and L3 cache.
implementation based on Intel’s 45 nanometer process, in the FC-mPGA8 package
with four or six processor cores and L3 cache.
• Processor core – Processor core with integrated L1 cache. The L2 cache is shared
between two cores on the die and interfaces to other processor pairs and the L3
cache through a simplified direct interface. All AC timing and signal integrity
specifications are at the pads of the processor die.
cache through a simplified direct interface. All AC timing and signal integrity
specifications are at the pads of the processor die.
• FC-mPGA8 — The Intel® Xeon® Processor 7400 Series is available in a Flip-Chip
Micro Pin Grid Array 8 package, consisting of a single processor die mounted on a
pinned substrate with an integrated heat spreader (IHS). This packaging
technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.
pinned substrate with an integrated heat spreader (IHS). This packaging
technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.
• mPGA604 — The Intel® Xeon® Processor 7400 Series processor mates with the
system board through this surface mount, 604-pin, zero insertion force (ZIF)
socket.
socket.
• FSB (Front Side Bus) – The electrical interface that connects the processor to the
chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Multi Independent Bus (MIB) – A front side bus architecture with one processor
on each bus, rather than a FSB shared between multiple processor agents. The MIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth.
architecture provides improved performance by allowing increased FSB speeds and
bandwidth.
• MTS - Mega Transfers per Second.
• Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum
• Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum
values the Intel® Xeon® Processor 7400 Series will have over certain time periods.
The values are only estimates and actual specifications for future processors may
differ.
The values are only estimates and actual specifications for future processors may
differ.
• Functional Operation – Refers to the normal operating conditions in which all
processor specifications, including DC, AC, FSB, signal quality, mechanical and
thermal are satisfied.
thermal are satisfied.
• Storage Conditions – Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor pins should not be connected
to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure
to “free air” (that is, unsealed packaging or a device removed from packaging
material) the processor must be handled in accordance with moisture sensitivity
labeling (MSL) as indicated on the packaging material.
exposed to free air. Under these conditions, processor pins should not be connected
to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure
to “free air” (that is, unsealed packaging or a device removed from packaging
material) the processor must be handled in accordance with moisture sensitivity
labeling (MSL) as indicated on the packaging material.
• Priority Agent – The priority agent is the host bridge to the processor and is
typically known as the chipset.