Intel E5503 AT80602003636AA Manual De Usuario
Los códigos de productos
AT80602003636AA
Features
132
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
Power-On Configuration (POC) logic levels are MUX-ed onto the VID[7:0] signals with
1-5 KΩ pull-up and pull-down resistors located on the baseboard. These include:
1-5 KΩ pull-up and pull-down resistors located on the baseboard. These include:
• VID[2:0] / MSID[2:0] = Market Segment ID
• VID[5:3] / CSC[2:0] = Current Sense Configuration
• VID[6] = Reserved
• VID[7] = VR11.1 Select
• VID[5:3] / CSC[2:0] = Current Sense Configuration
• VID[6] = Reserved
• VID[7] = VR11.1 Select
Pull-up and pull-down resistors on the baseboard eliminate the need for timing
specifications After the voltage regulator’s OUTEN signal is asserted, the VID[7:0]
CMOS drivers (typically 50Ω up / down impedance) override the POC pull-up / down
specifications After the voltage regulator’s OUTEN signal is asserted, the VID[7:0]
CMOS drivers (typically 50Ω up / down impedance) override the POC pull-up / down
resistors located on the baseboard and drive the necessary VID pattern. Please refer to
for further details.
7.2
Clock Control and Low Power States
The processor supports low power states at the individual thread, core, and package
level for optimal power management. The processor implements software interfaces for
requesting low power states: MWAIT instruction extensions with sub-state hints, the
HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block
mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to
equivalent MWAIT C-state requests inside the processor and do not directly result in
I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up
before using the P_LVLx I/O read interface.
level for optimal power management. The processor implements software interfaces for
requesting low power states: MWAIT instruction extensions with sub-state hints, the
HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block
mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to
equivalent MWAIT C-state requests inside the processor and do not directly result in
I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up
before using the P_LVLx I/O read interface.
Note:
Software may make C-state requests by using a legacy method involving I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
feature is designed to provide legacy support for operating systems that initiate C-state
transitions via access to pre-defined ICH registers. The base P_LVLx register is P_LVL2,
corresponding to a C3 request. P_LVL3 is C6, and all P_LVL4+ are demoted to a C6.
P_LVLx is limited to a subset of C-states supported on the processor (E.g., P_LVL8 is
not supported and will not cause an I/O redirection to a C8 request. Instead, it will fall
through like a normal I/O instruction). The range of I/O addresses that may be
converted into C-state requests is also defined in the PMG_IO_CAPTURE MSR, in the
not supported and will not cause an I/O redirection to a C8 request. Instead, it will fall
through like a normal I/O instruction). The range of I/O addresses that may be
converted into C-state requests is also defined in the PMG_IO_CAPTURE MSR, in the
Figure 7-1. PROCHOT# POC Timing Requirements
CPURESET#
Tri-State POC
(xxPROCHOT#)
BCLK
Min Hold (106)
Min Setup (2)
xxPROCHOT# deassertion is not required for FRB
Non-FRB assertion of
xxPROCHOT# during this window
can trigger false tri-state