Intel 2 Duo L7400 LE80537LF0214M Manual De Usuario
Los códigos de productos
LE80537LF0214M
Datasheet
15
Low Power Features
2.1.2
Package Low Power State Descriptions
2.1.2.1
Normal State
This is the normal operating state for the processor. The Intel Core 2 Duo mobile
processor remains in the Normal state when at least one of its cores is in the C0, C1/
AutoHALT, or C1/MWAIT state.
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted, each core of the Intel Core 2 Duo mobile processor
enters the Stop-Grant state within 20 bus clocks after the response phase of the
processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are
already in the C2, C3, or C4 state remain in their current low power state. When the
STPCLK# pin is deasserted, each core returns to its previous core low power state.
Note:
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to V
CCP
) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#,
SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to
RESET# deassertion (AC Specification T45). When re-entering the Stop-Grant state
from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the
deassertion of SLP# (AC Specification T75).
While in Stop-Grant state, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts
and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt or monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor
should return to the Normal state.
A transition to the Stop-Grant Snoop state will occur when the processor detects a
snoop on the FSB (see
). A transition to the Sleep state (see
) will occur with the assertion of the SLP# signal.
2.1.2.3
Stop-Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in Stop-
Grant state by entering the Stop-Grant Snoop state. The processor will stay in this
state until the snoop on the FSB has been serviced (whether by the processor or
another agent on the FSB) or the interrupt has been latched. The processor will return
to the Stop-Grant state once the snoop has been serviced or the interrupt has been
latched.
2.1.2.4
Sleep State
The Sleep state is a low power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#
pin should only be asserted when the processor is in the Stop-Grant state. SLP#
assertions while the processor is not in the Stop-Grant state is out of specification and
may result in unapproved operation.