Gateway Intel Xeon E5506 TC.32500.017 Manual De Usuario
Los códigos de productos
TC.32500.017
Register Description
50
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.6.1
MAXREQUEST_LC
Maximum requests expected from the chipset (number of TAD home trackers allocated
to chipset). The maximum RTID value that may be used is one less than this number.
Home trackers are allocated in groups of 8, so bits 2:0 of the register may not be
written, and bits 5:3 indicate how many groups of 8 are allocated.
to chipset). The maximum RTID value that may be used is one less than this number.
Home trackers are allocated in groups of 8, so bits 2:0 of the register may not be
written, and bits 5:3 indicate how many groups of 8 are allocated.
4
RO
TBD
Capability List (CLIST)
This bit is hardwired to “1” to indicate to the configuration software that this
This bit is hardwired to “1” to indicate to the configuration software that this
device/function implements a list of new capabilities. A list of new capabilities is
accessed via registers CAPPTR at the configuration address offset 34h from the
start of the PCI configuration space header of this function. Register CAPPTR
contains the offset pointing to the start address with configuration space of this
device where the capability register resides. This bit must be set for a PCI
Express device or if the VSEC capability.
If no capability structures are implemented, this bit is hardwired to 0.
If no capability structures are implemented, this bit is hardwired to 0.
3
RO
0
Interrupt Status:
If this device generates an interrupt, then this read-only bit reflects the state of
If this device generates an interrupt, then this read-only bit reflects the state of
the interrupt in the device/function. Only when the Interrupt Disable bit in the
command register is a 0 and this Interrupt Status bit is a 1, will the
device’s/function’s INTx# signal be asserted. Setting the Interrupt Disable bit to
a 1 has no effect on the state of this bit.
If this device does not generate interrupts, then this bit is not implemented (RO
If this device does not generate interrupts, then this bit is not implemented (RO
and reads returns 0).
2:0
RO
0
Reserved
Device:
0
Function:
0-1
Offset:
06h
Device:
2
Function:
0-1, 4-5
Offset:
06h
Device:
3
Function:
0-2, 4
Offset:
06h
Device:
4-6
Function:
0-3
Offset:
06h
Bit
Type
Reset
Value
Description
Device:
0
Function: 0
Offset:
40h
Access as a Dword
Bit
Type
Reset
Value
Description
5:3
RW
3
VALUE. Maximum TAD requests from chipset (allocated in groups of 8).