Nokia 6150 Manuales De Servicio
PAMS
Technical Documentation
NSM–1
System Module
Original 10/98
Page 3–54
DC Characteristics
Regulators
Transceiver has got a multi function power management IC, which con-
tains among other functions, also 7 pcs of 2.8 V regulators. All regulators
can be controlled individually with 2.8 V logic directly or through control
register. Direct controls are used to get fast switching, because regulators
are used to enable RF–functions.
tains among other functions, also 7 pcs of 2.8 V regulators. All regulators
can be controlled individually with 2.8 V logic directly or through control
register. Direct controls are used to get fast switching, because regulators
are used to enable RF–functions.
Use of the regulators can be seen in the power distribution diagram.
CCONT also provides 1.5 V reference voltage for SUMMA ( and for
DACs and ADCs in COBBA too ).
DACs and ADCs in COBBA too ).
Control Signals
All control signals are coming from MAD and they are 2.8 V logic signals.
Frequency synthesizers
Both UHF– and VHF–VCO are locked with PLLs into stable frequency
source, which is a VCTCXO–module ( voltage controlled temperature
compensated crystal oscillator ). Using VCTCXO, it is possible to leave
the center frequency and control curve slope calibration away in produc-
tion if needed.This VCTCXO is running at 13 MHz. Temperature effect is
controlled with AFC ( automatic frequency control ) voltage in order to
maintain VCTCXO locked into frequency of the base station. AFC is gen-
erated by baseband with a 11 bit DAC in COBBA–ASIC.
source, which is a VCTCXO–module ( voltage controlled temperature
compensated crystal oscillator ). Using VCTCXO, it is possible to leave
the center frequency and control curve slope calibration away in produc-
tion if needed.This VCTCXO is running at 13 MHz. Temperature effect is
controlled with AFC ( automatic frequency control ) voltage in order to
maintain VCTCXO locked into frequency of the base station. AFC is gen-
erated by baseband with a 11 bit DAC in COBBA–ASIC.
UHF PLL is located in SUMMA. There are 64/65 (P/P+1) prescaler, N–
and A–divider, reference divider, phase detector and charge pump for the
external loop filter. UHF local signal is generated by dividing the UHF–
VCO signal (there is only one UHF–VCO module, that is common for both
systems, running at 2GHz) by two in CRFU3 prescaler and from that the
signal is fed to SUMMA prescaler. Prescaler is a dual modulus divider.
Output of the prescaler is fed to N– and A–divider, which produce the in-
put to phase detector. Phase detector compares this signal to reference
signal, which is divided with reference divider from VCTCXO output. Out-
put of the phase detector is connected into charge pump, which charges
or discharges integrator capacitor in the loop filter depending on the
phase of the measured frequency compared to reference frequency. Loop
filter filters out the pulses and generates DC to control the frequency of
UHF–VCO. Loop filter defines step response of the PLL ( settling time )
and effects to stability of the loop, that’s why integrator capacitor has got
a resistor for phase compensation. Other filter components are for side-
band rejection.
Dividers are controlled via serial bus. SDATA is for data, SCLK is serial
clock for the bus and SENA1 is a latch enable, which stores new data into
and A–divider, reference divider, phase detector and charge pump for the
external loop filter. UHF local signal is generated by dividing the UHF–
VCO signal (there is only one UHF–VCO module, that is common for both
systems, running at 2GHz) by two in CRFU3 prescaler and from that the
signal is fed to SUMMA prescaler. Prescaler is a dual modulus divider.
Output of the prescaler is fed to N– and A–divider, which produce the in-
put to phase detector. Phase detector compares this signal to reference
signal, which is divided with reference divider from VCTCXO output. Out-
put of the phase detector is connected into charge pump, which charges
or discharges integrator capacitor in the loop filter depending on the
phase of the measured frequency compared to reference frequency. Loop
filter filters out the pulses and generates DC to control the frequency of
UHF–VCO. Loop filter defines step response of the PLL ( settling time )
and effects to stability of the loop, that’s why integrator capacitor has got
a resistor for phase compensation. Other filter components are for side-
band rejection.
Dividers are controlled via serial bus. SDATA is for data, SCLK is serial
clock for the bus and SENA1 is a latch enable, which stores new data into