Compaq iPAQ Internet Device Manual De Usuario
Chapter 5 Input/Output Interfaces
5-2 Compaq iPAQ Family of Internet Devices
First Edition – March 2000
Hard drives types not found in the ROM’s parameter table are automatically configured as to
(soft)type by DOS as follows:
(soft)type by DOS as follows:
Primary controller: drive 0, type 65; drive 1, type 66
Secondary controller: drive 0, type 68; drive 1, type 15
Secondary controller: drive 0, type 68; drive 1, type 15
Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive
configuration.
configuration.
5.2.1.1 IDE Configuration Registers
The IDE controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the IDE controller function (PCI device #31, function #1) are listed in
Table 5-1.
Table 5–1
configuration registers for the IDE controller function (PCI device #31, function #1) are listed in
Table 5-1.
Table 5–1
. IDE PCI Configuration Registers
Table 5-1.
EIDE PCI Configuration Registers (82801, Device 31/Function 1)
PCI Conf.
Addr.
Addr.
Register
Reset
Value
Value
PCI Conf.
Addr.
Addr.
Register
Reset
Value
Value
00-01h
Vender ID
8086h
24-2Bh
Reserved
0’s
02-03h
Device ID
2411h
2C, 2Dh
Subsystem Vender ID
8086h
04-05h
PCI Command
0000h
2E, 2Fh
Subsystem ID
2411h
06-07h
PCI Status
0280h
30-3Fh
Reserved
0’s
08h
Revision ID
00h
40-43h
Primary IDE Timing
0000h
09h
Programming
80h
44h
Secondary IDE Timing
00h
0Ah
Sub-Class
01h
48h
Sync. DMA Control
00h
0Bh
Base Class Code
01h
4A-4Bh
Sync. DMA Timing
0000h
0Dh
Master Latency Timer
0000h
54h
EIDE I/O Config.Register
00h
0Eh
Header Type
80h
F8-FBh
Manufacturer’s ID
0F-1Fh
Reserved
00h
FC-FFh
Reserved
20-23h
BMIDE Base Address
1h
--
--
--
NOTE:
Assume unmarked gaps are reserved and/or not used.
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table.
Table 5–2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table.
Table 5–2.
IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
Offset
Size
(Bytes)
Register
Default
Value
00h
1
Bus Master IDE Command (Primary)
00h
02h
1
Bus Master IDE Status (Primary)
00h
04h
4
Bus Master IDE Descriptor Pointer (Pri.)
0000 0000h
08h
1
Bus Master IDE Command (Secondary)
00h
0Ah
2
Bus Master IDE Status (Secondary)
00h
0Ch
4
Bus Master IDE Descriptor Pointer (Sec.)
0000 0000h
NOTE:
Unspecified gaps are reserved, will return indeterminate data, and should not be written to.