SMSC LAN9311 Manual De Usuario

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

240

SMSC LAN9311/LAN9311i

 

This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This
r e g i s t e r   i s   u s e d   i n   c o n j u n c t i o n   w i t h  

. The contents of this register are optionally loaded from the EEPROM at

power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant
byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM. The most significant byte
(bits [31:24]) is loaded from address 04h of the EEPROM. These EEPROM values are also loaded
into the 

. The Host can update the contents of this

field after the initialization process has completed.

 for details on how the EEPROM Loader loads

this register. Refer to 

 for information on using the

EEPROM Loader. 

Offset:

1F4h

Size:

32 bits

31:0

Physical Address[31:0]
This field contains the lower 32-bits (31:0) of the physical address of the 
Switch Fabric MACs.

R/W

FF0F8000h