SMSC LAN9311 Manual De Usuario

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

245

Revision 1.4 (08-19-08)

 

This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the 

 to perform write operations to the PHYs.

This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to

 for additional information.

Offset:

0A8h
EEPROM Loader 
Access Only

Size:

32 bits

31:16

RO

-

15:11

PHY Address (PHY_ADDR)
These bits select the PHY device being accessed. Refer to 

 for information on PHY address 

assignments.

WO

00000b

10:6

MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY. Refer to 

 for detailed 

descriptions on all PHY registers.

WO

00000b

5:2

RO

-

1

This bit must always be written with a value of 1.

WO

0b

0

RO

0b