SMSC USB2250 Manual De Usuario
Ultra Fast USB 2.0 Multi-Slot Flash Media Controller
Datasheet
Revision 1.1 (05-29-08)
14
SMSC USB2250/50i/51/51i
DATASHEET
SM Busy or Data
Ready
Ready
SM_nB/R
56
IPU
This pin is connected to the BSY/RDY pin of
the SM device.
the SM device.
When using the internal FET, this pin has an
internal weak pull-up resistor that is tied to
the output of the internal Power FET, and is
controlled by the SM_PU bit of the
SMC_CTL register.
internal weak pull-up resistor that is tied to
the output of the internal Power FET, and is
controlled by the SM_PU bit of the
SMC_CTL register.
If an external FET is used (Internal FET is
disabled), then the internal pull-up is not
available (external pull-ups must be used).
disabled), then the internal pull-up is not
available (external pull-ups must be used).
SM Chip Enable
SM_nCE
54
O12PU
This pin is the active low chip enable signal
to the SM device.
to the SM device.
When using the internal FET, this pin has an
internal weak pull-up resistor that is tied to
the output of the internal Power FET, and is
controlled by the SM_PU bit of the
SMC_CTL register.
internal weak pull-up resistor that is tied to
the output of the internal Power FET, and is
controlled by the SM_PU bit of the
SMC_CTL register.
If an external FET is used (Internal FET is
disabled), then the internal pull-up is not
available (external pull-ups must be used).
disabled), then the internal pull-up is not
available (external pull-ups must be used).
SM Card
Detection GPIO
Detection GPIO
GPIO14
(SM_nCD)
57
I/O12
This is a GPIO designated as the Smart
Media card detection pin.
Media card detection pin.
MEMORY STICK INTERFACE
MS Bus State
MS_BS
91
O12
This pin is connected to the BS pin of the MS
device.
device.
It is used to control the Bus States 0, 1, 2
and 3 (BS0, BS1, BS2 and BS3) of the MS
device.
and 3 (BS0, BS1, BS2 and BS3) of the MS
device.
MS Card
Insertion GPIO
Insertion GPIO
GPIO12
(MS_INS)
98
IPU
This is a GPIO designated as the Memory
Stick card detection pin.
Stick card detection pin.
MS System CLK
MS_SCLK
101
O12
This pin is an output clock signal to the MS
device.
device.
The clock frequency is software configurable.
MS System Data
In/Out
In/Out
MS_D[7:1] 100
97
93
95
99
96
92
93
95
99
96
92
I/O12PD
MS_D[7:0]: These pins are the bi-directional
data signals for the MS device. MS_D2 and
MS_D3 have weak pull-down resistors.
MS_D1 has a pull down resistor if it is in
parallel mode, otherwise it is disabled. In 4-
or 8-bit parallel mode, there is a weak pull-
down resistor on all MS_D7~0 signals. The
resistors are controlled by MSC_SYSTEM_0,
MSC_MODE_CTL and MSC_PRO_HG
registers.
data signals for the MS device. MS_D2 and
MS_D3 have weak pull-down resistors.
MS_D1 has a pull down resistor if it is in
parallel mode, otherwise it is disabled. In 4-
or 8-bit parallel mode, there is a weak pull-
down resistor on all MS_D7~0 signals. The
resistors are controlled by MSC_SYSTEM_0,
MSC_MODE_CTL and MSC_PRO_HG
registers.
Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)
NAME
SYMBOL
128-PIN
VTQFP
BUFFER
TYPE
DESCRIPTION