Hyundai gms90x52c Manual De Usuario
HYUNDAI MicroElectronics
GMS90X5XC Series
10
Jan. 2001 Ver 1.0
CPU
The GMS90X5XC series is efficient both as a controller and as an arithmetic processor. It has extensive facili-
ties for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory
results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With
a 12 MHz crystal, 58% of the instructions are executed in 1.0
ties for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory
results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With
a 12 MHz crystal, 58% of the instructions are executed in 1.0
µ
s (40MHz: 300ns).
Special Function Register PSW
Reset value of PSW is 00
H
.
Bit
Function
CY
Carry Flag
AC
Auxiliary Carry Flag (for BCD operations)
F0
General Purpose Flag
RS1
0
0
1
1
0
1
1
RS0
0
1
0
1
1
0
1
Register Bank select control bits
Bank 0 selected, data address 00
Bank 0 selected, data address 00
H
- 07
H
Bank 1 selected, data address 08
H
- 0F
H
Bank 2 selected, data address 10
H
- 17
H
Bank 3 selected, data address 18
H
- 1F
H
OV
Overflow Flag
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
CY
AC
F0
RS1 RS0 OV
F1
P
7
6
5
4
3
2
1
0
LSB
MSB
Bit No.
Addr. D0
H
PSW