Intel 41210 Manual De Usuario
82
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
Register Description
12.2.9
Offset 18h: BNUM—Bus Numbers
This register contains the primary, secondary, and maximum subordinate bus number registers.
12.2.10
Offset 1Bh: SMLT—Secondary Master Latency Timer
This timer controls the amount of time that the 41210 continues to burst data on its secondary
interface. The counter starts counting down from the assertion of FRAME#. When the grant is
removed, then the expiration of this counter results in the de-assertion of FRAME#. When the
grant is not removed, then the 41210 may continue ownership of the bus.
interface. The counter starts counting down from the assertion of FRAME#. When the grant is
removed, then the expiration of this counter results in the de-assertion of FRAME#. When the
grant is not removed, then the 41210 may continue ownership of the bus.
The secondary master
latency timer default value is 64 in PCI-X mode (see Section 8.6.1 of the PCI-X Addendum to the
PCI Local Bus Specification, Revision 1.0b).
PCI Local Bus Specification, Revision 1.0b).
Table 43.
Offset 18h: BNUM—Bus Numbers
Bits
Type
Reset
Description
23:16
RW
00h
Subordinate Bus Number (SBBN):
These bits indicate the highest PCI bus number
downstream of this bridge. Every Type 1 configuration cycle on PCI Express* with a bus
number greater than the secondary bus number and less than or equal to the subordinate
bus number is forwarded as a Type 1 configuration cycle to the secondary PCI bus.
number greater than the secondary bus number and less than or equal to the subordinate
bus number is forwarded as a Type 1 configuration cycle to the secondary PCI bus.
15:8
RW
00h
Secondary Bus Number (SCBN):
These bits indicate the bus number of the PCI device to
which the secondary interface is connected. Any Type 1 configuration cycle matching this
bus number is translated to a Type 0 configuration cycle and run on the PCI bus.
bus number is translated to a Type 0 configuration cycle and run on the PCI bus.
7:0
RW
00h
Primary Bus Number (PBN):
These bits indicate the PCI Express* bus number. Any
Type 1 configuration cycle with a bus number less than this number is not accepted by this
bridge (in other words, it may still match the other bridge).
bridge (in other words, it may still match the other bridge).
Table 44.
Offset 1Bh: SMLT—Secondary Master Latency Timer
Bits
Type
Reset
Description
7:3
RW
00h: PCI
40h: PCI-X
40h: PCI-X
Secondary Latency Timer (TV):
This 5-bit value indicates the number of PCI clocks, in
8-clock increments, during which the bridge remains as a master of the PCI bus when
another master is requesting use of the PCI bus.
another master is requesting use of the PCI bus.
2:0
RO
000b
Reserved