Intel 2 Extreme QX9650 BX80569QX9650A Manual De Usuario
Los códigos de productos
BX80569QX9650A
Electrical Specifications
30
Datasheet
.
2.7.3.2
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See
for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF.
lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
NOTES:
1.
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Variable
GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF
circuit may require different resistor values. Each GTLREF land must be connected.
GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF
circuit may require different resistor values. Each GTLREF land must be connected.
3.
R
TT
is the on-die termination resistance measured at V
TT
/3 of the GTL+ output driver.
4.
COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
COMP8 resistors are to V
COMP8 resistors are to V
SS
.
Table 2-12. PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
1
NOTES:
1. V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications. Refer
for V
TT
specifications.
V
in
Input Voltage Range
-0.15
V
TT
V
V
hysteresis
Hysteresis
0.1 * V
TT
—
V
2
2. The leakage specification applies to powered devices on the PECI bus.
V
n
Negative-edge threshold voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold voltage
0.550 * V
TT
0.725 * V
TT
V
I
source
High level output source
(V
(V
OH
= 0.75 * V
TT
)
-6.0
N/A
mA
I
sink
Low level output sink
(V
(V
OL
= 0.25 * V
TT
)
0.5
1.0
mA
I
leak+
High impedance state leakage to V
TT
N/A
50
µA
3
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
I
leak-
High impedance leakage to GND
N/A
10
µA
2
C
bus
Bus capacitance per node
—
10
pF
4
V
noise
Signal noise immunity above 300 MHz
0.1 * V
TT
—
V
p-p
Table 2-13. GTL+ Bus Resistance Definitions
Symbol
Parameter
Min
Typ
Max
Units Notes
1
GTLREF_PU GTLREF pull up resistor
57.6 * 0.99
57.6
57.6 * 1.01
Ω
2
GTLREF_PD GTLREF pull down resistor
100 * 0.99
100
100 * 1.01
Ω
2
R
TT
Termination Resistance
45
50
55
Ω
3
COMP[3:0]
COMP Resistance
49.40
49.90
50.40
Ω
4
COMP8
COMP Resistance
24.65
24.90
25.15
Ω
4