Simoco EMEA Ltd SDB670AC01 Manual De Usuario
SDB670 – SERVICE MANUAL
TNM-M-E-0032
May 13
Page 32
TECHNICAL DESCRIPTION
5.2.2.11
Analogue Inputs
The PMIC provides multiple analogue inputs which are currently used to provide voltage
monitoring of the unregulated supply.
monitoring of the unregulated supply.
5.2.2.12
GPS Input
The facilities connector provides an RS422 serial connection with a primary purpose of connecting
a GPS receiver to provide an accurate time stamp. An RS422 input is also provided for connection
of the 1PPS output from a GPS Rx to provide a very accurate reference clock to tune the internal
oscillator.
a GPS receiver to provide an accurate time stamp. An RS422 input is also provided for connection
of the 1PPS output from a GPS Rx to provide a very accurate reference clock to tune the internal
oscillator.
5.2.2.13
External Power
The control card provides the supply voltage at up to 1 A on the facilities connector.
5.2.2.14
RS232 Serial Interface (DB9)
The rear of the control card contains a standard 9-way serial connection in order that a straight
through cable may be used to provide debug and control data.
through cable may be used to provide debug and control data.
5.2.2.15
Expansion Header
An expansion header provides the necessary signals to support a multitude of future expansion
boards.
boards.
5.3 T
RANSMITTER AND
R
ECEIVER
M
ODULES
5.3.1
Control
Refer to Figure 10 (page 42) and Figures 2 and 3 in TNM-S-E-0005, SDM600 Series – Issue 4
Circuit Diagrams [2].
Circuit Diagrams [2].
5.3.1.1
DSP and FPGA
The SDM600 transceiver operates under the control of a DSP (U203) and Field Programmable
Gate Array (FPGA) (U300) combination that, together with a number of other dedicated devices,
perform all the operational and processing functions required by the radio, the software for which is
contained in flash memory. The FPGA contains an internal embedded processor core and
provides the majority of radio functionality, including demodulation, while the DSP provides most of
the complex filter and timing functions, a 57.6 MHz clock to the FPGA and ADC conversion. Both
the DSP and FPGA have internal Random Access Memory (RAM) for rapid code execution. In
addition, the FPGA utilizes external RAM contained in Cellular RAM U304 for increased capacity.
Gate Array (FPGA) (U300) combination that, together with a number of other dedicated devices,
perform all the operational and processing functions required by the radio, the software for which is
contained in flash memory. The FPGA contains an internal embedded processor core and
provides the majority of radio functionality, including demodulation, while the DSP provides most of
the complex filter and timing functions, a 57.6 MHz clock to the FPGA and ADC conversion. Both
the DSP and FPGA have internal Random Access Memory (RAM) for rapid code execution. In
addition, the FPGA utilizes external RAM contained in Cellular RAM U304 for increased capacity.
The FPGA in conjunction with the DSP provides the following functions:
•
Channel set-up of all operating frequencies.
•
Modulation processing and filtering.
•
De-modulation processing and filtering.
•
Tx power output.
•
Modulation equalisation adjustment.
•
Rx front-end tuning.
•
Serial communications with Alignment Tool and options including LVDS for microphone and
control head.
control head.
•
Modem functionality for data modulation.
•
All DMR/CTCSS/DCS generation and decoding.