Intel E7-2803 AT80615006438AB Manual De Usuario
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AT80615006438AB
Datasheet Volume 2 of 2
43
Power Management Architecture (Wbox)
9.2.2.2
Package C-State Resolution
The package must resolve the C-state requests of each core in order to determine the
proper package C-state. The C-state request is resolved by the Wbox to the lowest
numbered C-state requested by any of the enabled cores. If any core is in C0, the
resolved package C-state is C0. If no cores are in C0, and at least one core is in C1,
then C1 is the resolved package C-state, and so on. See the following table.
proper package C-state. The C-state request is resolved by the Wbox to the lowest
numbered C-state requested by any of the enabled cores. If any core is in C0, the
resolved package C-state is C0. If no cores are in C0, and at least one core is in C1,
then C1 is the resolved package C-state, and so on. See the following table.
9.2.2.3
Thread/Core C1/C1E Entry
C1/C1E entry can occur on execution of a HLT instruction or execution of an MWAIT
instruction with a C1 (or C1E) argument.
instruction with a C1 (or C1E) argument.
9.2.2.3.1
Thread/Core C1/C1E Exit
A thread in the C1/C1E state will wake up when an interrupt directed to that core
arrives at the local APIC. The APIC will send the wakeup event to the thread if the
event is not masked in the APIC LVT or EFLAGS.IF. When the thread wakes up,
hardware will set the active bit for that core in the Wbox.
arrives at the local APIC. The APIC will send the wakeup event to the thread if the
event is not masked in the APIC LVT or EFLAGS.IF. When the thread wakes up,
hardware will set the active bit for that core in the Wbox.
9.2.2.3.2
C1E Specific Details
A C1 request will be interpreted as a C1E request in two cases. First, the MWAIT
instruction can be invoked with an argument that specifically requests a C1E transition.
Additionally, IA32_MISC_ENABLES MSR, is used to indicate that all C1 transitions
should be converted to C1E requests.
instruction can be invoked with an argument that specifically requests a C1E transition.
Additionally, IA32_MISC_ENABLES MSR, is used to indicate that all C1 transitions
should be converted to C1E requests.
9.2.2.3.3
Package C1/C1E
If all enabled cores in the package have requested a C1E transition, then the Wbox will
initiate a voltage and frequency change to the minimum operating V/f point. When any
thread exits C1E, the woken thread will begin execution at this minimum operating V/f
point as soon as the event reaches the core.
initiate a voltage and frequency change to the minimum operating V/f point. When any
thread exits C1E, the woken thread will begin execution at this minimum operating V/f
point as soon as the event reaches the core.
9.2.2.4
C3
9.2.2.4.1
Thread/Core C3 Entry
C3 entry can occur on execution of an MWAIT instruction with a C3 argument, or via an
I/O read to the P_LVL2 address. The request will result in the execution of a flow, which
will clean up the state of the machine, write the C-state target control register in the
uncore (Wbox) with the core specific request (if this is the last thread to run the C-state
flow), and then put the thread to sleep. If this is the first thread to leave C0 on an SMT
enabled part, the partitioned resources will be re-partitioned on C1/C1E entry. When all
enabled threads are sleeping, core hardware will clear the core active bit in the C-state
target control register in the Wbox.
I/O read to the P_LVL2 address. The request will result in the execution of a flow, which
will clean up the state of the machine, write the C-state target control register in the
uncore (Wbox) with the core specific request (if this is the last thread to run the C-state
flow), and then put the thread to sleep. If this is the first thread to leave C0 on an SMT
enabled part, the partitioned resources will be re-partitioned on C1/C1E entry. When all
enabled threads are sleeping, core hardware will clear the core active bit in the C-state
target control register in the Wbox.
Table 9-2.
Package C-State Resolution
If Any Core Is In
Then Package Resolved C-State Is
C0
C0
C1, and no cores are in C0
C1
C3, and no cores are in C0, C1, or C1E
C3
C6 and no threads are in C0, C1, C1E, or C3
C6