Getac Technology Corporation V110GD Manual De Usuario

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© 2011 Microchip Technology Inc.
Preliminary
DS61168C-page 159
PIC32MX1XX/2XX
14.0
INPUT CAPTURE
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement. 
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause
capture events:
1.
Simple capture event modes
-  Capture timer value on every falling edge of 
input at ICx pin
-  Capture timer value on every rising edge of 
input at ICx pin
2.
Capture timer value on every edge (rising and
falling)
3.
Capture timer value on every edge (rising and
falling), specified edge first.
4.
Prescaler capture event modes
- Capture timer value on every 4th rising 
edge of input at ICx pin
- Capture timer value on every 16th rising 
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
Other operational features include:
• Device wake-up from capture pin during CPU 
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
Interrupt optionally generated after 1, 2, 3 or 4 
buffer locations are filled
• Input capture can also be used to provide 
additional sources of external interrupts
FIGURE 14-1:
INPUT CAPTURE BLOCK DIAGRAM 
Note 1:
This data sheet summarizes the features
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input
Capture”
 (DS61122) of the “PIC32
Family Reference Manual”
, which is
www.microchip.com/PIC32
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
 in
this data sheet for device-specific register
and bit information.
Note:
 An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
FIFO CONTROL
ICxBUF
TMR2 TMR3
CaptureEvent
/N
FIFO
ICI<1:0>
ICM<2:0>
ICM<2:0>
101
100
011
010
001
001
111
To CPU
Set Flag ICxIF
(In IFSx Register)
Rising Edge Mode
Prescaler Mode 
(4th Rising Edge)
Falling Edge Mode
Edge Detection 
Prescaler Mode 
(16th Rising Edge)
Sleep/Idle
Wake-up Mode
C32/ICTMR
ICx pin
 
 
Mode
110
Specified/Every 
Edge Mode
FEDGE