Getac Technology Corporation V110GD Manual De Usuario
PIC32MX1XX/2XX
DS61168C-page 188
Preliminary
© 2011 Microchip Technology Inc.
REGISTER 19-2:
PMMODE: PARALLEL PORT MODE REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
BUSY
IRQM<1:0>
INCM<1:0>
—
MODE<1:0>
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAITB<1:0>
(1)
WAITM<3:0>
(1)
WAITE<1:0>
(1)
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 15
BUSY:
Busy bit (Master mode only)
1
= Port is busy
0
= Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11
= Reserved, do not use
10
= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only)
01
= Interrupt generated at the end of the read/write cycle
00
= No Interrupt generated
bit 12-11 INCM<1:0>: Increment Mode bits
11
= Slave mode read and write buffers auto-increment (PMMODE<1:0> = 00 only)
10
= Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle
(2)
01
= Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle
(2)
00
= No increment or decrement of address
bit 10
Unimplemented:
Read as ‘0’
bit 9-8
MODE<1:0>:
Parallel Port Mode Select bits
11
= Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA<x:0>, and PMD<7:0>)
10
= Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>)
01
= Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>)
00
= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>)
bit 7-6
WAITB<1:0>:
Data Setup to Read/Write Strobe Wait States bits
(1)
11
= Data wait of 4 T
PB
; multiplexed address phase of 4 T
PB
10
= Data wait of 3 T
PB
; multiplexed address phase of 3 T
PB
01
= Data wait of 2 T
PB
; multiplexed address phase of 2 T
PB
00
= Data wait of 1 T
PB
; multiplexed address phase of 1 T
PB
(default)
Note 1:
Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 T
PBCLK
cycle for a
write operation; WAITB = 1 T
PBCLK
cycle, WAITE = 0 T
PBCLK
cycles for a read operation.
2:
Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.