Getac Technology Corporation V110GD Manual De Usuario
© 2011 Microchip Technology Inc.
Preliminary
DS61168C-page 197
PIC32MX1XX/2XX
bit 7-0
ARPT<7:0>:
Alarm Repeat Counter Value bits
(3)
11111111
= Alarm will trigger 256 times
•
•
•
•
•
00000000
= Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
REGISTER 20-2:
RTCALRM: RTC ALARM CONTROL REGISTER
(1)
(CONTINUED)
Note 1:
This register is reset only on a Power-on Reset (POR).
2:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
CHIME = 0.
3:
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
4:
This assumes a CPU read will execute in less than 32 PBCLKs.