Intel E3-1220L CM8062307262828 Manual De Usuario
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CM8062307262828
Signal Description
64
Datasheet, Volume 1
6.1
System Memory Interface
Table 6-2.
Memory Channel A
Signal Name
Description
Direction/
Buffer Type
SA_BS[2:0]
Bank Select: These signals define which banks are selected within
each SDRAM rank.
each SDRAM rank.
O
DDR3
SA_WE#
Write Enable Control Signal: This signal is used with SA_RAS# and
SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
O
DDR3
SA_RAS#
RAS Control Signal: This signal is used with SA_CAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
(along with SA_CS#) to define the SRAM Commands.
O
DDR3
SA_CAS#
CAS Control Signal: This signal is used with SA_RAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
(along with SA_CS#) to define the SRAM Commands.
O
DDR3
SA_DQS[8:0]
SA_DQS#[8:0]
Data Strobes: SA_DQS[8:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write
transactions.
up a differential strobe pair. The data is captured at the crossing point
of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write
transactions.
I/O
DDR3
SA_DQ[63:0]
Data Bus: Channel A data signal interface to the SDRAM data bus.
I/O
DDR3
SA_ECC_CB[7:0]
ECC Data Lines: Data Lines for ECC Check Byte.
I/O
DDR3
SA_MA[15:0]
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
row and column address to the SDRAM.
O
DDR3
SA_CK[3:0]
SDRAM Differential Clock: Channel A SDRAM Differential clock signal
pair. The crossing of the positive edge of SA_CK and the negative edge
of its complement SA_CK# are used to sample the command and
control signals on the SDRAM.
pair. The crossing of the positive edge of SA_CK and the negative edge
of its complement SA_CK# are used to sample the command and
control signals on the SDRAM.
O
DDR3
SA_CK#[3:0]
SDRAM Inverted Differential Clock: Channel A SDRAM Differential
clock signal-pair complement.
clock signal-pair complement.
O
DDR3
SA_CKE[3:0]
Clock Enable: (1 per rank). Used to:
Initialize the SDRAMs during power-up
Power-down SDRAM ranks
Place all SDRAM ranks into and out of self-refresh during STR
O
DDR3
SA_CS#[3:0]
Chip Select: (1 per rank). Used to select particular SDRAM
components during the active state. There is one Chip Select for each
SDRAM rank.
components during the active state. There is one Chip Select for each
SDRAM rank.
O
DDR3
SA_ODT[3:0]
On Die Termination: Active Termination Control.
O
DDR3