CALAMP WIRELESS NETWORKS INC. BDD4T881 Manual De Usuario
120 20170-200
Paragon
PD
Technical Manual
12
This feature is exclusive to the Series II
model. Series I model’s programming is
done externally via EPROMs.
model. Series I model’s programming is
done externally via EPROMs.
•
DB-25M plug at PL1 (one side of the “Y”
cable on each PCB) – used to supply the re-
ceive signal to the BDLC
ceive signal to the BDLC
PD
’s single
“EXT.RADIO/TEST” DB-25F plug.
•
Two channel-select DIP switches (SW1 and
SW2)
This feature is exclusive to the Series II
model.
model.
•
Cooling fan driver – CN2 located on back-
plane connects to the horizontally-mounted
fan on top of the Radio assembly and acti-
vated by BDLC’s PTT signal.
fan on top of the Radio assembly and acti-
vated by BDLC’s PTT signal.
•
Coaxial relay driver – not used.
3.2 BDLC
PD
The rack-mounted BDLC
PD
is housed in a steel
case. It has no user serviceable parts. Unit’s con-
figuration is stored in flash memory (EEPROM).
figuration is stored in flash memory (EEPROM).
3.2.1 BDLC
PD
Front panel
Referring to Figure 2, the front panel of the
BDLC
BDLC
PD
has two cutouts across its length.
A- The left cutout groups the unit’s type label
and ten LED indicators:
and ten LED indicators:
•
The S3 label designates the BDLC
PD
as a
“three Serial-port” model
(Ports 4 and 5 are reserved for future use)
(Ports 4 and 5 are reserved for future use)
•
The RF group of 3 LEDs
•
The RS-232 group of 5 LEDs
•
A single CK LED
•
The ALARMS group of 4 LEDs
B- The right cutout groups two tactile (mem-
brane) switches (PF1 and RESET).
brane) switches (PF1 and RESET).
3.2.1.1 Front
Switches
Referring to Figure 11, the BDLC
PD
uses two
membrane-type switches labeled:
•
RESET
•
PF 1
These switches indicate contact by emitting a
short BEEP tone when pressed.
short BEEP tone when pressed.
Figure 11 - BDLC
PD
membrane switches
3.2.1.1.1 Reset
Pressing Reset produces the same result as pow-
ering OFF and ON again. It restarts the micro-
processor, the peripherals and invokes the on-
board diagnostics. BDLC
ering OFF and ON again. It restarts the micro-
processor, the peripherals and invokes the on-
board diagnostics. BDLC
PD
’s radio modules’
internal flash-memories are read and their values
are loaded in system SRAM CPU flash-memory.
are loaded in system SRAM CPU flash-memory.
Normally, pressing Reset results in one short
BEEP tone followed by all LEDs coming ON for
about four seconds. Then, the LEDs flash in a
“ripple” pattern for close to two seconds indi-
cating diagnostics are in progress. At the end of
this period, all LEDs should be OFF except CK
that should flash about six to eight times per
second.
BEEP tone followed by all LEDs coming ON for
about four seconds. Then, the LEDs flash in a
“ripple” pattern for close to two seconds indi-
cating diagnostics are in progress. At the end of
this period, all LEDs should be OFF except CK
that should flash about six to eight times per
second.
Expect an additional two seconds delay for CK
to start flashing and the UF indicator to come
ON if the radio assembly is not connected or not
powered (see section 3.2.1.2.4 for Alarm de-
tails).
to start flashing and the UF indicator to come
ON if the radio assembly is not connected or not
powered (see section 3.2.1.2.4 for Alarm de-
tails).
3.2.1.1.2 PF
1
PF 1 is a multi-function switch:
•
It clears LED error indications
•
It initiates test transmissions
•
It sets the function of the RS-232 LEDs
PF1
RESET