Compal Electronics Inc PICONODE Manual De Usuario
PicoNode Integration Specification
25
MRQ=1
Node
SRDY=1
Host
Slave
Request
Slave Ready
ArbREQ
ArbACK
ValREQ
ValACK
ValACK
Arbitration
Request
Arbitration
Acknowledge
Validation
Acknowledge
Validation
Request
Request
MMsgREQ+ Size
MMsgACK + Size
MMsgACK + Size
MHdrREQ
MHdrAC K
MHdrAC K
Master Message
Request
Master Message
Acknowledge
Master Header
Request
Master Header
Acknowledge
Payload
Transmit
Payload
Receive
Receive
SMsgREQ+ Size
SMsgACK + Size
SHdrREQ
SHdrACK
SHdrACK
Slave Message
Request
Slave Message
Acknowledge
Slave Header
Request
Slave Header
Acknowledge
Acknowledge
Payload
Transmit
Payload
Receive
Receive
Repeat 6 steps above
PAYLOAD
SRQ=1
Slave
Request
Arbitration
Host-to- Node
Message
Transfer
Node-to- Host
Message
Transfer
wait
wait
wait
wait
wait
wait
wait
= Turn-around Delay
MRQ=1
SRDY=1
MRQ=1
SRDY=1
wait
wait
PAYLOAD
Repeat 5 steps above
if needed
Figure 1 SPI Master and Slave Message Sequences
In each of the request/acknowledge command pairs shown, the top command is transmitted by
the Host (master) and the bottom command is transmitted by the Node (slave). The wait
bubbles indicate a predefined turn-around delay which provides ISR processing time and avoids
race conditions between Host and Node.
the Host (master) and the bottom command is transmitted by the Node (slave). The wait
bubbles indicate a predefined turn-around delay which provides ISR processing time and avoids
race conditions between Host and Node.