BEI Electronics LLC 7EPTX-AM5E Manual De Usuario
1-17
1-77.
High Reflected Power Release Signal. A reflected power release signal is controlled by
AND gate U38A. When condition causing the high forward/reflected power condition is
removed, a HIGH operate signal, a HIGH 1.2 : 1 VSWR signal from comparator U66C,
and a HIGH from latch U67A will be ANDed at U38A. U38A will respond by routing a
HIGH reflected power release signal to priority encoder U28. U28 will respond by
routing a binary number to multiplexer U27. U27 will respond by selecting a clock signal
from integrated circuit U26. U26 is a divider designed to generate several clock signals.
The clock signals are used to drive the power control circuit up/down counters up as
determined by the type of release signal applied to U28. For example, a high reflected
power release condition selects a 2 Hz clock signal. The 2 Hz clock signal from U27 is
applied to up/down counters U30/U31. U30/U31 will respond by counting up and routing
binary numbers to digital-to-analog converter U42. U42 will respond by routing an
increased voltage reference to U43. U43 will output an increased reference voltage to
increase the transmitter output power.
1-78.
Over-Temperature Recovery. When the condition which caused the over-temperature
problem is removed, the transmitter will initiate a recovery sequence.
The output of
comparator U65A will go LOW. The LOW is applied to AND gate U51D. With a HIGH
enable failure signal, U51D will output a LOW to terminate the over-temperature attack
signal.
1-79.
When the temperature is reduced to approximately 55 degrees C, the output of
comparator U65B will go HIGH. The HIGH is applied to AND gate U47D. With the
HIGH from latch U67C, U47D will output a HIGH over-temperature release signal to
priority encoder U28. U28 will respond by routing a binary number to multiplexer U27.
U27 will respond by selecting a 1/16 Hz clock signal from integrated circuit U26. The
1/16 Hz clock signal from U27 is applied to up/down counters U30/U31. U30/U31 will
respond by counting up and routing binary numbers to digital-to-analog converter U42.
U42 will respond by routing an increased voltage reference to U43. U43 will output an
increased reference voltage to increase the transmitter output power.
1-80.
Reflected Power Emergency/Lightning Recovery. When the condition which caused the
reflected power emergency/lightning problem is removed, the transmitter will initiate a
recovery sequence.
The sequence is initiated by comparator U65D. U65D compares a fast
reflected power voltage sample to a reference voltage. When the sample voltage is below
the reference, the output of U65D will go HIGH. The HIGH is applied to AND gate
U71A. With a HIGH from latch U67B, U71A will output a fast foldback release signal to
priority encoder U28. U28 will respond by routing a binary number to multiplexer U27.
U27 will respond by selecting a 512 Hz clock signal from integrated circuit U26. The 512
Hz clock signal from U27 is applied to up/down counters U30/U31. U30/U31 will respond
by counting up and routing binary numbers to digital-to-analog converter U42. U42 will
respond by routing an increased voltage reference to U43. U43 will output an increased
reference voltage to increase the transmitter output power.
1-81.
In addition to the sequence initiated by U65D, a HIGH foldback reset command is applied
to transistor Q56. The HIGH biases Q56 on to unlatch OR gate U69C. U69C will output
a LOW to latch U49A to allow the latch to be reset.
1-82.
EXCITER MONITORING.
The operating condition of the exciter is monitored by a exciter
status circuit. During an exciter fault condition, the exciter fault status input will go
HIGH. The HIGH is applied to AND gate U36D. With a HIGH enable failure signal,
U36D will output a HIGH to latch U48A. U48A will output a HIGH to: 1) bias driver
transistor Q45 off to extinguish the exciter indicator green LED and 2) inverter U46A.
U46A will output a LOW to bias driver transistor Q44 on. This will illuminate the
exciter indicator red LED.