Intel III Xeon 500 MHz 80525KX500512 Manual De Usuario
Los códigos de productos
80525KX500512
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
95
9.1.42
RP# (I/O)
The RP# (Request Parity) signal is driven by the request initiator, and provides parity protection on
ADS# and REQ[4:0]#. It must connect the appropriate pins of all Pentium
ADS# and REQ[4:0]#. It must connect the appropriate pins of all Pentium
III
Xeon processor
system bus agents.
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered signals
are high.
number of covered signals are low. This definition allows parity to be high when all covered signals
are high.
9.1.43
RS[2:0]# (I)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction), and must connect the appropriate pins of all Pentium
completion of the current transaction), and must connect the appropriate pins of all Pentium
III
Xeon processor system bus agents.
9.1.44
RSP# (I)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP#
provides parity protection. It must connect the appropriate pins of all Pentium
completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP#
provides parity protection. It must connect the appropriate pins of all Pentium
III
Xeon processor
system bus agents.
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it
is not being driven by any agent guaranteeing correct parity.
number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it
is not being driven by any agent guaranteeing correct parity.
9.1.45
SA[2:0] (I)
The SA (Select Address) pins are decoded on the SMBus in conjunction with the upper address bits
in order to maintain unique addresses on the SMBus in a system with multiple Pentium
in order to maintain unique addresses on the SMBus in a system with multiple Pentium
III
Xeon
processors. To set an SA line high, a pull-up resistor should be used that is no larger than 1 k
Ω
. To
set an SA line as low, SA1 and SA0 can be left unconnected; to set SA2 as low, it should be pulled
to ground (~10 k
to ground (~10 k
Ω
). SA2 can also be tri-stated to define additional addresses for the thermal sensor.
A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Of the addresses broadcast across the SMBus, the memory components claim those of the form
“1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent
addresses. The Y bit is hard-wired on the cartridge to V
“1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent
addresses. The Y bit is hard-wired on the cartridge to V
SS
(‘0’) for the Scratch EEPROM and
pulled to V
CCSMB
US
(‘1’) for the Processor Information ROM. The “XX” bits are defined by the
processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled
down weakly (10 k
down weakly (10 k
Ω
) on the cartridge to ensure that the memory components are in a known state
in systems which do not support the SMBus, or only support a partial implementation. The “Z” bit
is the read/write bit for the serial bus transaction.
is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented,
includes a Hi-Z state for one address pin (SA2), and therefore supports 6 unique resulting
addresses. The ability of the system to drive this pin to a Hi-Z state is dependent on the baseboard
implementation (The pin must be left floating). The system should drive SA1 and SA0, and will be
pulled low (if not driven) by the 10k
“0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented,
includes a Hi-Z state for one address pin (SA2), and therefore supports 6 unique resulting
addresses. The ability of the system to drive this pin to a Hi-Z state is dependent on the baseboard
implementation (The pin must be left floating). The system should drive SA1 and SA0, and will be
pulled low (if not driven) by the 10k
Ω
pull-down resistor on the processor substrate. Driving these