Cisco 8GB DDR3-1333 A02-M308GD5-2 Manual De Usuario

Each CPU controls four serial memory interface (SMI) channels (see 

). There is one 

memory riser for every two channels. There are therefore two memory risers per CPU. Each CPU channel 
drives a memory buffer on a riser card, and each memory buffer converts a CPU SMI into two DDR3 
subchannels that each read and write two DIMM pairs on a memory riser. 

The physical layout of a memory riser is shown in 

.

In 

, the buffers and channels are:

■

Buffer 1, subchannel 1: slots 1B and 1D

■

Buffer 1, subchannel 2: slots 1A and 1C

■

Buffer 2, subchannel 1: slots 2B and 2D

■

Buffer 2, subchannel 2: slots 2A and 2C

When considering the memory configuration of your server, you should observe the following: 

■

The minimum configuration for the server is at least one matched DIMM pair installed in a 
memory riser on either CPU1 or CPU2 All four CPUs can run from a single DIMM pair.

■

DIMMs are required to be populated in pairs. DIMMs for this server are configured as 
two-DIMM kits.

Memory buffer #1

Memory buffer #2

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