Intel i7-3920XM Extreme AW8063801009607 Manual De Usuario
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AW8063801009607
Processor Configuration Registers
90
Datasheet, Volume 2
2.6.4
PCISTS—PCI Status Register
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express* bridge embedded within the Root port.
the "virtual" Host-PCI Express* bridge embedded within the Root port.
1
RW
0b
Uncore
Memory Access Enable (MAE)
0 = All of device's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address
0 = All of device's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address
ranges defined in the MBASE, MLIMIT, PMBASE, and
PMLIMIT registers.
0
RW
0b
Uncore
IO Access Enable (IOAE)
0 = All of device’s I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE, and
0 = All of device’s I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE, and
IOLIMIT registers.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
4–5h
Reset Value:
0000h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
00h
Bit
Access
Reset
Value
RST/
PWR
Description
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
6–7h
Reset Value:
0010h
Access:
RO, RW1C, RO-V
Size:
16 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
15
RW1C
0b
Uncore
Detected Parity Error (DPE)
This bit is set by a Function whenever it receives a Poisoned TLP,
This bit is set by a Function whenever it receives a Poisoned TLP,
regardless of the state the Parity Error Response bit in the
Command register. On a Function with a Type 1 Configuration
header, the bit is set when the Poisoned TLP is received by its
Primary Side.
Reset Value of this bit is 0b.
This bit will be set only for completions of requests encountering
Reset Value of this bit is 0b.
This bit will be set only for completions of requests encountering
ECC error in DRAM.
Poisoned peer-to-peer posted forwarded will not set this bit. They
Poisoned peer-to-peer posted forwarded will not set this bit. They
are reported at the receiving port.
14
RW1C
0b
Uncore
Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to detecting
This bit is set when this Device sends an SERR due to detecting
an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable
bit in the Command register is '1'. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do not affect
this field.
13
RO
0b
Uncore
Received Master Abort Status (RMAS)
This bit is set when a Requester receives a Completion with
This bit is set when a Requester receives a Completion with
Unsupported Request Completion Status. On a Function with a
Type 1 Configuration header, the bit is set when the Unsupported
Request is received by its Primary Side.
Not applicable. UR not on primary interface.
Not applicable. UR not on primary interface.