Intel i7-3920XM Extreme AW8063801009607 Manual De Usuario
Los códigos de productos
AW8063801009607
Processor Configuration Registers
198
Datasheet, Volume 2
2.10.42 SLOTCTL—Slot Control Register
Note:
PCI Express* Hot-Plug is not supported on the processor.
B/D/F/Type:
0/6/0/PCI
Address Offset:
B8–B9h
Reset Value:
0000h
Access:
RO
Size:
16 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
15:13
RO
0h
Reserved (RSVD)
12
RO
0b
Uncore
Reserved for Data Link Layer State Changed Enable
(DLLSCE)
If the Data Link Layer Link Active capability is implemented, when
If the Data Link Layer Link Active capability is implemented, when
set to 1b, this field enables software notification when Data Link
Layer Link Active field is changed.
If the Data Link Layer Link Active capability is not implemented,
If the Data Link Layer Link Active capability is not implemented,
this bit is permitted to be read-only with a value of 0b.
11
RO
0b
Uncore
Reserved for Electromechanical Interlock Control (EIC)
If an Electromechanical Interlock is implemented, a write of 1b to
If an Electromechanical Interlock is implemented, a write of 1b to
this field causes the state of the interlock to toggle. A write of 0b
to this field has no effect. A read to this register always returns a
0.
10
RO
0b
Uncore
Reserved for Power Controller Control (PCC)
If a Power Controller is implemented, this field when written sets
If a Power Controller is implemented, this field when written sets
the power state of the slot per the defined encodings. Reads of
this field must reflect the value from the latest write, even if the
corresponding hot-plug command is not complete, unless
software issues a write without waiting for the previous command
to complete in which case the read value is undefined.
Depending on the form factor, the power is turned on/off either to
Depending on the form factor, the power is turned on/off either to
the slot or within the adapter. Note that in some cases the power
controller may autonomously remove slot power or not respond to
a power-up request based on a detected fault condition,
independent of the Power Controller Control setting.
The defined encodings are:
0 = Power On
1 = Power Off
If the Power Controller Implemented field in the Slot Capabilities
The defined encodings are:
0 = Power On
1 = Power Off
If the Power Controller Implemented field in the Slot Capabilities
register is set to 0b, then writes to this field have no effect and
the read value of this field is undefined.
9:8
RO
00b
Uncore
Reserved Power Indicator Control (PIC)
If a Power Indicator is implemented, writes to this field set the
If a Power Indicator is implemented, writes to this field set the
Power Indicator to the written state. Reads of this field must
reflect the value from the latest write, even if the corresponding
hot-plug command is not complete, unless software issues a write
without waiting for the previous command to complete in which
case the read value is undefined.
00 = Reserved
01 = On
10 = Blink
11 = Off
If the Power Indicator Present bit in the Slot Capabilities register
00 = Reserved
01 = On
10 = Blink
11 = Off
If the Power Indicator Present bit in the Slot Capabilities register
is 0b, this field is permitted to be read-only with a value of 00b.