Intel i7-3920XM Extreme AW8063801009607 Manual De Usuario
Los códigos de productos
AW8063801009607
Datasheet, Volume 2
267
Processor Configuration Registers
2.18.4
GCMD_REG—Global Command Register
This register controls remapping hardware. If multiple control fields in this register
need to be modified, software must serialize the modifications through multiple writes
to this register.
need to be modified, software must serialize the modifications through multiple writes
to this register.
0
RO
0b
Uncore
Coherency (C)
This field indicates if hardware access to the root, context, page-
This field indicates if hardware access to the root, context, page-
table and interrupt-remap structures are coherent (snooped) or
not.
0 = Hardware accesses to remapping structures are non-
0 = Hardware accesses to remapping structures are non-
coherent.
1 = Hardware accesses to remapping structures are coherent.
Hardware access to advanced fault log and invalidation queue are
Hardware access to advanced fault log and invalidation queue are
always coherent.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
10–17h
Reset Value:
0000000000F0101Ah
Access:
RO, RO-V
Size:
64 bits
BIOS Optimal Default
00000000000h
Bit
Access
Reset
Value
RST/
PWR
Description
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
18–1Bh
Reset Value:
00000000h
Access:
RO, WO
Size:
32 bits
BIOS Optimal Default
000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31
WO
0b
Uncore
Translation Enable (TE)
Software writes to this field to request hardware to
Software writes to this field to request hardware to
enable/disable DMA-remapping:
0 = Disable DMA remapping
1 = Enable DMA remapping
Hardware reports the status of the translation enable operation
0 = Disable DMA remapping
1 = Enable DMA remapping
Hardware reports the status of the translation enable operation
through the TES field in the Global Status register.
There may be active DMA requests in the platform when software
There may be active DMA requests in the platform when software
updates this field. Hardware must enable or disable remapping
logic only at deterministic transaction boundaries, so that any in-
flight transaction is either subject to remapping or not at all.
Hardware implementations supporting DMA draining must drain
Hardware implementations supporting DMA draining must drain
any in-flight DMA read/write requests queued within the Root-
Complex before completing the translation enable command and
reflecting the status of the command through the TES field in the
Global Status register.
The value returned on a read of this field is undefined.
The value returned on a read of this field is undefined.