Intel i7-3920XM Extreme AW8063801009607 Manual De Usuario
Los códigos de productos
AW8063801009607
Datasheet, Volume 2
49
Processor Configuration Registers
2.5.2
DID—Device Identification Register
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
PCI device.
2.5.3
PCICMD—PCI Command Register
Since Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
implemented.
B/D/F/Type:
0/0/0/PCI
Address Offset:
2–3h
Reset Value:
0150h
Access:
RO-FW, RO-V
Size:
16 bits
Bit
Access
Reset
Value
RST/
PWR
Description
15:4
RO-FW
015h
Uncore
Device Identification Number MSB (DID_MSB)
This is the upper part of device identification assigned to the
This is the upper part of device identification assigned to the
processor.
3:2
RO-V
00b
Uncore
Device Identification Number SKU (DID_SKU)
This is the middle part of device identification assigned to the
This is the middle part of device identification assigned to the
processor.
1:0
RO-FW
00b
Uncore
Device Identification Number LSB (DID_LSB)
This is the lower part of device identification assigned to the
This is the lower part of device identification assigned to the
processor.
B/D/F/Type:
0/0/0/PCI
Address Offset:
4–5h
Reset Value:
0006h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
00h
Bit
Access
Reset
Value
RST/
PWR
Description
15:10
RO
0h
Reserved (RSVD)
9
RO
0b
Uncore
Fast Back-to-Back Enable (FB2B)
This bit controls whether or not the master can do fast back-to-
This bit controls whether or not the master can do fast back-to-
back write. Since Device 0 is strictly a target this bit is not
implemented and is hardwired to 0. Writes to this bit position
have no effect.
8
RW
0b
Uncore
SERR Enable (SERRE)
This bit is a global enable bit for Device 0 SERR messaging. The
This bit is a global enable bit for Device 0 SERR messaging. The
processor communicates the SERR condition by sending an SERR
message over DMI to the PCH.
1 = The processor is enabled to generate SERR messages over
1 = The processor is enabled to generate SERR messages over
DMI for specific Device 0 error conditions that are
individually enabled in the ERRCMD and DMIUEMSK
registers. The error status is reported in the ERRSTS,
PCISTS, and DMIUEST registers.
0 = The SERR message is not generated by the Host for Device
0.
This bit only controls SERR messaging for Device 0. Other
integrated devices have their own SERRE bits to control error
reporting for error conditions occurring in each device. The
control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
0 = Device 0 SERR disabled
1 = Device 0 SERR enabled
0 = Device 0 SERR disabled
1 = Device 0 SERR enabled