HP DL580 G7 E7-4830 2P 64GB-R P410i/512 FBWC 2x1200W 643065R-421 Manual De Usuario
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643065R-421
NOTE: Memory configurations listed do not apply to "Factory Integrated Models".
HP ProLiant DL580 G7
Memory Subsystem Architecture
Intel® Xeon® processor E7 and 7500 series memory architecture is designed to take advantage of multiple stages of memory
interleaving to reduce latency and increase bandwidth.
Intel® Xeon® processor E7 and 7500 series memory architecture is designed to take advantage of multiple stages of memory
interleaving to reduce latency and increase bandwidth.
Each processor contains two Memory Controllers as shown in the Processor/Memory interconnect figure below. Each Memory
controller has two Scalable Memory Interface (SMI) buses operating in lockstep where each SMI bus connects to a memory buffer. The
purpose of the buffer is to convert SMI to DDR3. Each buffer has two DDR3 channels and can support up to four DIMMs for a total of
eight DIMMs per cartridge.
controller has two Scalable Memory Interface (SMI) buses operating in lockstep where each SMI bus connects to a memory buffer. The
purpose of the buffer is to convert SMI to DDR3. Each buffer has two DDR3 channels and can support up to four DIMMs for a total of
eight DIMMs per cartridge.
Memory speed is not affected by number of DIMMs or ranks. All DIMMs will run at the highest possible speed for a given
processor.
DDR3 memory speed is a function of the processors QPI bus speed such that
processor.
DDR3 memory speed is a function of the processors QPI bus speed such that
Processors with a QPI speed of 6.4GT will run memory at 1066MHz
Processors with a QPI speed of 5.6GT will run memory at 978MHz
Processors with a QPI speed of 4.8GT will run memory at 800 MHz
Processors with a QPI speed of 5.6GT will run memory at 978MHz
Processors with a QPI speed of 4.8GT will run memory at 800 MHz
DIMM Installation guidelines
Each memory cartridge can support up to 8 DIMMs, for a system total of 64 DIMMs. When installing DIMM modules in the Memory
Cartridge observe the following minimum guidelines:
Each memory cartridge can support up to 8 DIMMs, for a system total of 64 DIMMs. When installing DIMM modules in the Memory
Cartridge observe the following minimum guidelines:
UDIMMs are not supported
Minimum allowable configuration is two DIMMs per cartridge.
DIMMs must be installed in pairs with identical characteristics. For configuration simplicity HP recommends using identical part
numbered DIMMs throughout when possible.
DIMM pairs MUST be populated in sequence by letter designation. Install DIMM pair 1A, 8A first followed by DIMM pair 3B, 6B then
DIMM pair 2C, 7C and DIMM pair 4D, 5D last.
Maximum performance is achieved by balancing DIMM pairs by letter groupings across all memory cartridges. Such that the 1A,
8A pair is install in all memory cartridges first (see diagram below) followed by the B pair, C pair and D pair.
AMP modes Online Sparing and Memory Mirroring have further requirements beyond these listed here. Please refer to the user
guide for additional memory configuration requirements.
Minimum allowable configuration is two DIMMs per cartridge.
DIMMs must be installed in pairs with identical characteristics. For configuration simplicity HP recommends using identical part
numbered DIMMs throughout when possible.
DIMM pairs MUST be populated in sequence by letter designation. Install DIMM pair 1A, 8A first followed by DIMM pair 3B, 6B then
DIMM pair 2C, 7C and DIMM pair 4D, 5D last.
Maximum performance is achieved by balancing DIMM pairs by letter groupings across all memory cartridges. Such that the 1A,
8A pair is install in all memory cartridges first (see diagram below) followed by the B pair, C pair and D pair.
AMP modes Online Sparing and Memory Mirroring have further requirements beyond these listed here. Please refer to the user
guide for additional memory configuration requirements.
Figure 1 Processor/Memory interconnect
Illustration of how the processor, cartridges and DIMMs are electrically connected.
QuickSpecs
HP ProLiant DL580 Generation 7 (G7)
Memory
DA - 13669 Worldwide — Version 35 — September 24, 2012
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