Intel G645 BX80623G645 Manual De Usuario
Los códigos de productos
BX80623G645
Datasheet, Volume 2
121
Processor Configuration Registers
3
RW1C
0b
Uncore
Presence Detect Changed (PDC)
A pulse indication that the inband presence detect state has
A pulse indication that the inband presence detect state has
changed
This bit is set when the value reported in Presence Detect State is
This bit is set when the value reported in Presence Detect State is
changed.
2
RO
0b
Uncore
Reserved for MRL Sensor Changed (MSC)
If an MRL sensor is implemented, this bit is set when a MRL Sensor
If an MRL sensor is implemented, this bit is set when a MRL Sensor
state change is detected. If an MRL sensor is not implemented, this
bit must not be set.
1
RO
0b
Uncore
Reserved for Power Fault Detected (PFD)
If a Power Controller that supports power fault detection is
If a Power Controller that supports power fault detection is
implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware
capability, it is possible that a power fault can be detected at any
time, independent of the Power Controller Control setting or the
occupancy of the slot. If power fault detection is not supported,
this bit must not be set.
0
RO
0b
Uncore
Reserved for Attention Button Pressed (ABP)
If an Attention Button is implemented, this bit is set when the
If an Attention Button is implemented, this bit is set when the
attention button is pressed. If an Attention Button is not
supported, this bit must not be set.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
BA–BBh
Reset Value:
0000h
Access:
RO, RO-V, RW1C
Size:
16 bits
BIOS Optimal Default
00h
Bit
Attr
Reset
Value
RST/
PWR
Description