Intel G645 BX80623G645 Manual De Usuario
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BX80623G645
Processor Configuration Registers
228
Datasheet, Volume 2
27
RO
0b
Uncore
Write Buffer Flush (WBF)
This bit is valid only for implementations requiring write buffer
This bit is valid only for implementations requiring write buffer
flushing.
Software sets this field to request that hardware flush the Root-
Software sets this field to request that hardware flush the Root-
Complex internal write buffers. This is done to ensure any updates
to the memory-resident remapping structures are not held in any
internal write posting buffers.
Hardware reports the status of the write buffer flushing operation
Hardware reports the status of the write buffer flushing operation
through the WBFS field in the Global Status register.
Clearing this bit has no effect. The value returned on a read of this
Clearing this bit has no effect. The value returned on a read of this
field is undefined.
26
WO
0b
Uncore
Queued Invalidation Enable (QIE)
This field is valid only for implementations supporting queued
This field is valid only for implementations supporting queued
invalidations.
Software writes to this field to enable or disable queued
Software writes to this field to enable or disable queued
invalidations.
0 = Disable queued invalidations.
0 = Disable queued invalidations.
1 = Enable use of queued invalidations.
Hardware reports the status of queued invalidation enable
Hardware reports the status of queued invalidation enable
operation through QIES field in the Global Status register.
The value returned on a read of this field is undefined.
The value returned on a read of this field is undefined.
25
WO
0b
Uncore
Interrupt Remapping Enable (IRE)
This field is valid only for implementations supporting interrupt
This field is valid only for implementations supporting interrupt
remapping.
0 = Disable interrupt-remapping hardware
0 = Disable interrupt-remapping hardware
1 = Enable interrupt-remapping hardware
Hardware reports the status of the interrupt remapping enable
Hardware reports the status of the interrupt remapping enable
operation through the IRES field in the Global Status register.
There may be active interrupt requests in the platform when
There may be active interrupt requests in the platform when
software updates this field. Hardware must enable or disable
interrupt-remapping logic only at deterministic transaction
boundaries, so that any in-flight interrupts are either subject to
remapping or not at all.
Hardware implementations must drain any in-flight interrupt
Hardware implementations must drain any in-flight interrupt
requests queued in the Root-Complex before completing the
interrupt-remapping enable command and reflecting the status of
the command through the IRES field in the Global Status register.
The value returned on a read of this field is undefined.
The value returned on a read of this field is undefined.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
18–1Bh
Reset Value:
0000_0000h
Access:
RO, WO
Size:
32 bits
BIOS Optimal Default
000000h
Bit
Attr
Reset
Value
RST/
PWR
Description