Intel G645 BX80623G645 Manual De Usuario
Los códigos de productos
BX80623G645
Datasheet, Volume 2
291
Processor Configuration Registers
2.21.24 IEDATA_REG—Invalidation Event Data Register
This register specifies the Invalidation Event interrupt message data. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
2.21.25 IEADDR_REG—Invalidation Event Address Register
This register specifies the Invalidation Event Interrupt message address. This register
is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
A4–A7h
Reset Value:
0000_0000h
Access:
RW-L
Size:
32 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
31:16
RW-L
0000h
Uncore
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data
Hardware implementations supporting only 16-bit interrupt data
treat this field as Rsvd.
15:0
RW-L
0000h
Uncore
Interrupt Message data (IMD)
Data value in the interrupt request.
Data value in the interrupt request.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
A8–ABh
Reset Value:
0000_0000h
Access:
RW-L
Size:
32 bits
BIOS Optimal Default
0h
Bit
Attr
Reset
Value
RST/
PWR
Description
31:2
RW-L
00000000h
Uncore
Message address (MA)
When fault events are enabled, the contents of this register specify
When fault events are enabled, the contents of this register specify
the DWORD-aligned address (bits 31:2) for the interrupt request.
1:0
RO
0h
Reserved