Intel i3-3130M AW8063801111500 Manual De Usuario

Datasheet, Volume 1

45

The processor introduces a software visible random number generation mechanism 
supported by a high quality entropy source. This capability will be made available to 
programmers through the new RDRAND instruction. The resultant random number 
generation capability is designed to comply with existing industry standards in this 
regard (ANSI X9.82 and NIST SP 800-90).

Some possible usages of the new RDRAND instruction include cryptographic key 
generation as used in a variety of applications including communication, digital 
signatures, secure storage, and so on.

The Intel x2APIC architecture extends the xAPIC architecture that provides key 
mechanism for interrupt delivery. This extension is intended primarily to increase 
processor addressability.

Specifically, x2APIC:

• Retains all key elements of compatibility to the xAPIC architecture:

— delivery modes
— interrupt and processor priorities
— interrupt sources
— interrupt destination types

• Provides extensions to scale processor addressability for both the logical and 

physical destination modes

• Adds new features to enhance performance of interrupt delivery
• Reduces complexity of logical destination mode interrupt delivery on link based 

architectures

The key enhancements provided by the x2APIC architecture over xAPIC are the 
following:

• Support for two modes of operation to provide backward compatibility and 

extensibility for future platform innovations:

— In xAPIC compatibility mode, APIC registers are accessed through memory 

mapped interface to a 4

 

KB page, identical to the xAPIC architecture.

— In x2APIC mode, APIC registers are accessed through Model Specific Register 

(MSR) interfaces. In this mode, the x2APIC architecture provides significantly 

increased processor addressability and some enhancements on interrupt 

delivery.

• Increased range of processor addressability in x2APIC mode:

— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt 

processor addressability up to 4

  GB-1 processors in physical destination mode. 

A processor implementation of x2APIC architecture can support fewer than 

32

 

bits in a software transparent fashion.

— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC 

ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit logical ID 

within the cluster. Consequently, ((2^20) -16) processors can be addressed in 

logical destination mode. Processor implementations can support fewer than 

16

 

bits in the cluster ID sub-field and logical ID sub-field in a software agnostic 

fashion.