Intel G1620T CM8063701448300 Manual De Usuario
Los códigos de productos
CM8063701448300
PCI Express* 2.0
702
Datasheet
Events and interrupts that are handled by the root port are shown with the possible
interrupts they can deliver to the interrupt decoder/router.
interrupts they can deliver to the interrupt decoder/router.
Note:
lists the possible interrupts and events generated based on Packets received,
or events generated in the root port. Configuration needed by software to enable the
different interrupts as applicable.
different interrupts as applicable.
When INTx interrupts are received by an end point, they are mapped to the following
interrupts and sent to the interrupt decoder/router in the iLB:
interrupts and sent to the interrupt decoder/router in the iLB:
Note:
Interrupts generated from events within the root port are not swizzled.
17.2.2.1
Express Card Hot Plug Events
Express Card Hot Plug is available based on Presence Detection for each root port.
Note:
A full Hot Plug Controller is not implemented.
Presence detection occurs when a PCI Express* device is plugged in and power is
supplied. The physical layer will detect the presence of the device, and the root port will
set the SLSTS.PDS and SLSTS.PDC bits.
supplied. The physical layer will detect the presence of the device, and the root port will
set the SLSTS.PDS and SLSTS.PDC bits.
When a device is removed and detected by the physical layer, the root port will clear
the SLSTS.PDS bit, and set the SLSTS.PDC bit.
the SLSTS.PDS bit, and set the SLSTS.PDC bit.
Interrupts can be generated by the root port when a hot plug event occurs. A hot plug
event is defined as the transition of the SLSTS.PDC bit from 0 to 1. Software can set
the SLCTL.PDE and SLTCTL.HPE bits to allow hot plug events to generate an interrupt.
event is defined as the transition of the SLSTS.PDC bit from 0 to 1. Software can set
the SLCTL.PDE and SLTCTL.HPE bits to allow hot plug events to generate an interrupt.
Table 125. Possible Interrupts Generated From Events/Packets
Packet/Event
Type
INTx
MSI
SERR
SCI
SMI
GPE
INTx
Packet
X
X
PM_PME
Packet
X
X
Power Management (PM)
Event
X
X
X
X
Hot Plug (HP)
Event
X
X
X
X
ERR_CORR
Packet
X
ERR_NONFATAL
Packet
X
ERR_FATAL
Packet
X
Internal Error
Event
X
VDM
Packet
X
Table 126. Interrupt Generated for INT[A-D] Interrupts
INTA
INTB
INTC
INTD
Root Port 1
INTA#
INTB#
INTC#
INTD#
Root Port 2
INTD#
INTA#
INTB#
INTC#
Root Port 3
INTC#
INTD#
INTA#
INTB#
Root Port 4
INTB#
INTC#
INTD#
INTA#