Intel E7-8891 v2 CM8063601377422 Manual De Usuario
Los códigos de productos
CM8063601377422
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
139
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.4.19 TCOTHP
Timing Constraints DDR3 Other Timing Parameter.
5:3
RW
0x2
T_RRDD (t_rrdd):
Back to back READ to READ from different DIMM separation parameter. The
actual READ to READ command separation is TRRDD + 5 DCLKs measured
between the clock assertion edges of the two corresponding asserted
command CS#. Note that the minimum setting of the field must meet the
DDRIO requirement for READ to READ turnaround time to be at least 5 DClk
at the DDRIO pin.
The maximum design range from the above calculation is 31.
2:0
RW
0x2
T_RRDR (t_rrdr):
Back to back READ to READ from different RANK separation parameter. The
actual READ to READ command separation is TRRDR + 5 DCLKs measured
between the clock assertion edges of the two corresponding asserted
command CS#. Note that the minimum setting of the field must meet the
DDRIO requirement for READ to READ turnaround time to be at least 5 DClk
at the DDRIO pin.
The maximum design range from the above calculation is 31.
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x208
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x20c
Bit
Attr
Default
Description
31:28
RW
0x6
t_cs_oe:
When t_cs_oe = 0, CS[9:0]# will not tristate
Otherwise, this field defines delay in Dclks to disable CS output after all CKE
Otherwise, this field defines delay in Dclks to disable CS output after all CKE
pins are low
27:24
RW
0x6
t_odt_oe:
When t_odt_oe = 0, ODT will not tristate
Otherwise, this field defines delay in Dclks to disable ODT output after all CKE
Otherwise, this field defines delay in Dclks to disable ODT output after all CKE
pins are low and either in self-refresh or in IBTOff mode
23:20
RV
-
Reserved
19:16
RV
-
Reserved
15:12
RW
0x2
t_rwdr:
11:11
RW
0x0
shift_odt_early:
This shifts the ODT waveform one cycle early relative to the timing set up in the
ODT_TBL2 register, when in 2N or 3N mode.
This bit has no effect in 1N mode.
This bit has no effect in 1N mode.